CS5530 datasheet(180/241 Pages) NSC

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Revision 4.1

Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers

Bit

Description

Offset 00h-01h

Top Level SMI Status Mirror Register (RO)

Reset Value = 0000h

Suspend Modulation Enable Mirror (Read Only): This bit mirrors the Suspend Mode Configuration bit (F0 Index

96h[0]). It is used by the SMI handler to determine if the SMI Speedup Disable Register (F1BAR+Memory Offset 08h)

must be cleared on exit.

SMI SourceisUSB (Read Only): SMI was caused by USB activity? 0 = No; 1 = Yes.

SMI generation is configured in F0 Index 42h[7:6].

SMI Source is Warm Reset Command (Read Only): SMI was caused by Warm Reset command? 0 = No; 1 = Yes.

SMI SourceisNMI (Read Only): SMI was caused by NMI activity? 0 = No; 1 = Yes.

11:10

Reserved (Read Only): Always reads 0.

SMI Source is General Purpose Timers/User Defined Device Traps/Register Space Trap (Read Only): SMI was

caused by expiration of GP Timer 1/2; trapped access to UDEF3/2/1; trapped access to F1-F4 or ISA Legacy Register

Space? 0 = No; 1 = Yes.

The next level of status is found at F1BAR+Memory Offset 04h/06h.

SMI Source is Software Generated (Read Only): SMI was caused by software? 0 = No; 1 = Yes.

SMIonanA20M# Toggle (Read Only): SMI was caused by an access to either Port 092h or the keyboard command

which initiates an A20M# SMI? 0 = No; 1 = Yes.

This method of controlling the internal A20M# in the GXLV processor is used instead of a pin.

SMI generation enabling is at F0 Index 53h[0].

SMI Source is a VGA Timer Event (Read Only): SMI was caused by the expiration of the VGA Timer

(F0 Index 8Eh)? 0 = No; 1 = Yes.

SMI generation enabling is at F0 Index 83h[3].

SMI Source is Video Retrace (IRQ2) (Read Only): SMI was caused by a video retrace event as decoded from the serial

connection (PSERIAL register, bit 7) from the GXLV processor? 0 = No; 1 = Yes.

SMI generation enabling is at F0 Index 83h[2].

4:2

Reserved (Read Only): Always reads 0.

SMI Source is Audio Interface (Read Only): SMI was caused by the audio interface? 0 = No; 1 = Yes.

The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h.

SMI Source is Power Management Event (Read Only): SMI was caused by one of the power management resources?

0= No; 1 = Yes.

The next level of status is found at F0 Index 84h-87h/F4h-F7h.

Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9.

Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 02h.

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