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CS5530 数据表(PDF) 208 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 208 Page - National Semiconductor (TI) |
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208 / 241 page  www.national.com 208 Revision 4.1 Register Descriptions (Continued) 4.5 ISA LEGACY I/O REGISTER SPACE The bit formats for the ISA Legacy I/O Registers plus two chipset-specific configuration registers used for interrupt mapping in the CS5530 Core Logic are given in this sec- tion. These registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/output instructions (i.e., CPU direct R/W) with the designated I/O port address and 8-bit data. The registers are separated into the following categories: • DMA Channel Control Registers, see Table 4-25 • DMA Page Registers, see Table 4-26 • Programmable Interval Timer Registers, see Table 4-27 • Programmable Interrupt Controller Registers, see Table 4-28 • Keyboard Controller Registers, see Table 4-29 • Real Time Clock Registers, see Table 4-30 • Miscellaneous Registers, see Table 4-31 (includes 4D0h and 4D1h Interrupt Edge/Level Select Registers and ACPI Timer Count Register at I/O Port 121Ch) Table 4-25. DMA Channel Control Registers Bit Description I/O Port 000h (R/W) DMA Channel 0 Address Register Written as two successive bytes, byte 0, 1. I/O Port 001h (R/W) DMA Channel 0 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 002h (R/W) DMA Channel 1 Address Register Written as two successive bytes, byte 0, 1. I/O Port 003h (R/W) DMA Channel 1 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 004h (R/W) DMA Channel 2 Address Register Written as two successive bytes, byte 0, 1. I/O Port 005h (R/W) DMA Channel 2 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 006h (R/W) DMA Channel 3 Address Register Written as two successive bytes, byte 0, 1. I/O Port 007h (R/W) DMA Channel 3 Transfer Count Register Written as two successive bytes, byte 0, 1. I/O Port 008h (R/W) Read DMA Status Register, Channels 3:0 7 Channel 3 Request: Request pending? 0 = No; 1 = Yes. 6 Channel 2 Request: Request pending? 0 = No; 1 = Yes. 5 Channel 1 Request: Request pending? 0 = No; 1 = Yes. 4 Channel 0 Request: Request pending? 0 = No; 1 = Yes. 3 Channel 3 Terminal Count: TC reached? 0 = No; 1 = Yes. 2 Channel 2 Terminal Count: TC reached? 0 = No; 1 = Yes. 1 Channel 1 Terminal Count: TC reached? 0 = No; 1 = Yes. 0 Channel 0 Terminal Count: TC reached? 0 = No; 1 = Yes. Write DMA Command Register, Channels 3:0 7 DACK Sense: 0= Active high; 1= Active low. 6 DREQ Sense: 0 = Active high; 1 = Active low. 5 Write Selection: 0 = Late write; 1 = Extended write. 4 Priority Mode: 0 = Fixed; 1 = Rotating. 3 Timing Mode: 0 = Normal; 1 = Compressed. 2 Channels 3:0: 0 = Disable; 1 = Enable. 1:0 Reserved: Set to 0. |
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