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USB CONTROLLER REGISTERS - PCIUSB

The registers designated as PCIUSB are 32-bit registers

decoded from the PCI address bits 7 through 2 and

C/BE[3:0]#, when IDSEL is high, AD[10:8] select the

appropriate function, and AD[1:0] are '00'. Bytes within a

32-bit address are selected with the valid byte enables. All

registers can be accessed via 8-, 16-, or 32-bit cycles

(i.e., each byte is individually selected by the byte

enables.) Registers marked as reserved, and reserved

bits within a register are not implemented and should

return 0s when read. Writes have no effect for reserved

registers. Table4-24gives thebit formatsfor theUSB

controller’s PCI configuration registers.

Table 4-24. PCIUSB Index xxh: USB Controller Registers

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 0E11h

Index 02h-03h

Device Identification Register (RO)

Reset Value = A0F8h

Index 04h-05h

Command Register (R/W)

Reset Value = 0000h

15:10

Reserved: Set to 0.

Fast Back-to-Back Enable (Read Only): USB only acts as a master to a single device, so this functionality is not

needed. It is always disabled (must always be set to 0).

SERR#: USB asserts SERR# when it detects an address parity error: 0 = Disable; 1 = Enable.

Wait Cycle Control: USB does not need to insert a wait state between the address and data on the AD lines. It is always

disabled (bit is set to 0).

Parity Error: USB asserts PERR# when it is the agent receiving data and it detects a data parity error:

0 = Disable; 1 = Enable.

VGA Palette Snoop Enable (Read Only): USB does not support this function. It is always disabled (bit is set to 0).

Memory Write and Invalidate: Allow USB to run Memory Write and Invalidate commands: 0 = Disable; 1 = Enable.

The Memory Write and Invalidate Command will only occur if the cacheline size is set to 32 bytes and the memory write

is exactly one cache line.

If the CS5530 is being used in a GXLV processor based system, this bit must be set to 0.

Special Cycles: USB does not run special cycles on PCI. It is always disabled (bit is set to 0).

PCI Master Enable: Allow USB to run PCI master cycles: 0 = Disable; 1 = Enable.

Memory Space: Allow USB to respond as a target to memory cycles: 0 = Disable; 1 = Enable.

I/O Space: Allow USB to respond as a target to I/O cycles: 0 = Disable; 1 = Enable.

Index 06h-07h

Status Register (R/W)

Reset Value = 0280h

Detected Parity Error: This bit is set whenever the USB detects a parity error, even if the Parity Error (Response) Detec-

tion Enable Bit (Command Register, bit 6) is disabled. Write 1 to clear.

SERR# Status: This bit is set whenever the USB detects a PCI address error. Write 1 to clear.

Received Master Abort Status: This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory cycle.

Write 1 to clear.

Received Target Abort Status: This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted by a

PCI target. Write 1 to clear.

Signaled Target Abort Status: This bit is set whenever the USB signals a target abort. Write 1 to clear.

10:9

DEVSEL# Timing (Read Only): These bits indicate the DEVSEL# timing when performing a positive decode. Since

DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b.

Data Parity Reported: Set to 1 if the Parity Error Response bit (Command Register bit 6) is set, and USB detects PERR#

asserted while acting as PCI master (whether PERR# was driven by USB or not).

Fast Back-to-Back Capable: USB does support fast back-to-back transactions when the transactions are not to the

same agent. This bit is always 1.

6:0

Reserved: Set to 0.

Note: The PCI Specification defines this register to record status information for PCI related events. This is a read/write register.

However, writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location

is a 1.

Index 08h

Device Revision ID Register (RO)

Reset Value = 00h

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