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CS5530 数据表(PDF) 202 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 202 Page - National Semiconductor (TI) |
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202 / 241 page  www.national.com 202 Revision 4.1 Register Descriptions (Continued) Offset 0Ch-0Fh Video Y Register (R/W) Reset Value = xxxxxxxxh 31:27 Reserved: Set to 0. 26:16 VideoYEndPosition: This field represents the vertical end position of the video window according to the following for- mula: Position programmed = screen position + (V_TOTAL – V_SYNC_END) + 1. 15:11 Reserved: Set to 0. 10:0 Video Y Start Position: This field represents the vertical start position of the video window according to the following for- mula: Position programmed = screen position + (V_TOTAL – V_SYNC_END) + 1. Offset 10h-13h Video Scale Register (R/W) Reset Value = xxxxxxxxh 31:30 Reserved: Set to 0. 29:16 Video Y Scale Factor: This field represents the video window vertical scale factor according to the following formula: VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1) Where: Ys = Video Source vertical size in lines Yd = Video Destination vertical size in lines 15:14 Reserved: Set to 0. 13:0 Video X Scale Factor: This field represents the video window horizontal scale factor according to the following formula: VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1) Where: Xs = Video Source horizontal size in pixels Xd = Video Destination horizontal size in pixels Offset 14h-17h Video Color Key Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Video Color Key: This field represents the video color key. It is a 24-bit RGB value. The graphics or video data being compared may be masked prior to the compare by programming the Video Color Mask Register (F4BAR+Memory Offset 18h) appropriately. Offset 18h-1Bh Video Color Mask Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Video Color Mask: This field represents the video color mask. It is a 24-bit RGB value. Zeroes in the mask cause the corresponding bits in the graphics or video stream being compared to be ignored. Offset 1Ch-1Fh Palette Address Register (R/W) Reset Value = xxxxxxxxh 31:8 Reserved: Set to 0. 7:0 Palette Address: The value programmed is used to initialize the palette address counter. Offset 20h-23h Palette Data Register (R/W) Reset Value = xxxxxxxxh 31:24 Reserved: Set to 0. 23:0 Palette Data: This register contains the read or write data for a Gamma RAM access. Offset 24h-27h DOT Clock Configuration Register (R/W) Reset Value = 00000000h 31 Reset: Reset the PLL: 0 = Normal operation; 1 = Reset 30 Half Clock: 0 = Enable; 1 = Disable. For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post divider output to more closely approximate a 50% output duty cycle. 29 Reserved: Set to 0. Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued) Bit Description |
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