CS5530 datasheet(198/241 Pages) NSC

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198

Revision 4.1

Offset 41h

Audio Bus Master 4 SMI Status Register (RC)

Reset Value = 00h

Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot).

7:4

Reserved (Read to Clear)

Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first?

0= No; 1 = Yes.

If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to

pause until this register is read to clear the error.

End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)?

0= No; 1 = Yes.

Note: Must be read and written as a BYTE.

Offset 42h-43h

Not Used

Offset 44h-47h

Audio Bus Master 4 PRD Table Address (R/W)

Reset Value = 00000000h

Audio Bus Master 4: Output to Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[19] selects slot).

31:2

Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 4.

When written, this register points to the first entry in a PRD table. Once Audio Bus Master 4 is enabled (Command Regis-

ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.

When read, this register points to the next PRD.

1:0

Reserved: Set to 0.

Offset 48h

Audio Bus Master 5 Command Register (R/W)

Reset Value = 00h

Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot).

7:4

Reserved: Set to 0. Must return 0 on reads.

Read or Write Control: Set the transfer direction of Audio Bus Master 5: 0 = PCI reads performed;

1 = PCI writes performed.

This bit must be set to 1 (write) and should not be changed when the bus master is active.

2:1

Reserved: Set to 0. Must return 0 on reads.

Bus Master Control: Controls the state of the Audio Bus Master 5: 0 = Disable; 1 = Enable.

Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be

either paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior

including the possibility of the bus master state machine crashing. The only recovery from this condition is a PCI reset.

Note: Must be read and written as a BYTE.

Offset 49h

Audio Bus Master 5 SMI Status Register (RC)

Reset Value = 00h

Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot).

7:4

Reserved (Read to Clear)

Bus Master Error (Read to Clear): Hardware encountered a second EOP before software has cleared the first?

0= No; 1 = Yes.

If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to

pause until this register is read to clear the error.

End of Page (Read to Clear): Bus master transferred data which is marked by EOP bit in the PRD table (bit 30)?

0= No; 1 = Yes.

Note: Must be read and written as a BYTE.

Offset 4Ah-4Bh

Not Used

Offset 4Ch-4Fh

Audio Bus Master 5 PRD Table Address (R/W)

Reset Value = 00000000h

Audio Bus Master 5: Input from Codec; 16-Bit; Slot 6 or 11 (F3BAR+Memory Offset 08h[20] selects slot).

31:2

Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for Audio Bus Master 5.

When written, this register points to the first entry in a PRD table. Once Audio Bus Master 5 is enabled (Command Regis-

ter bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.

When read, this register points to the next PRD.

1:0

Reserved: Set to 0.

Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers (Continued)

Bit

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