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Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers

Bit

Description

Offset 00h-03h

Video Configuration Register (R/W)

Reset Value = 00000000h

Reserved: Set to 0

High Speed Timing for Video Interface: High speed timings for the video interface: 0 = Disable; 1= Enable.

If bit 30 is enabled, bit 25 should be set to 0.

16-bit Video Interface: Allow video interface to be 16 bits: 0 = Disable; 1= Enable.

If bit 29 is enabled, 8 bits of pixel data is used for video. The 24-bit pixel data is then dithered to 16 bits.

Note: F4BAR+Memory Offset 04h[25] should be set to the same value as this bit (bit 29).

YUV 4:2:2 or 4:2:0 Mode: 0 = 4:2:2 Mode; 1= 4:2:0 Mode.

If 4:2:0 mode is selected, bits [3:2] should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode.

Note: The GXLV processor does not support 4:2:0 mode.

Video Line Size (DWORDs): This is the MSB of the Video Line Size (DWORDs). See bits [15:8] for description.

Reserved: Set to 0

Early Video Ready: Generate VID_RDY output signal one-half VID_CLK period early to improve the speed of the video

port operation: 0 = Disable; 1 = Enable.

If bit 30 is enabled, this bit (bit 25) should be set to 0.

Initial Buffer Read Address: This is the MSB of the Initial Buffer Read Address. See bits [23:16] for description.

23:16

Initial Buffer Read Address: This field is used to preload the starting read address for the line buffers at the beginning of

each display line. It is used for hardware clipping of the video window at the left edge of the active display. It represents

the DWORD address of the source pixel which is to be displayed first. For an unclipped window, this value should be 0.

15:8

Video Line Size (DWORDs): This field represents the horizontal size of the source video data in DWORDs.

YFilter Enable: Vertical filter: 0 = Disable; 1= Enable.

XFilter Enable: Horizontal filter: 0 = Disable; 1 = Enable.

CSC Bypass: Allows color-space-converter to be bypassed. Primarily used for displaying an RGB graphics overlay rather

than a YUV video overlay. 0 = Overlay data passes through CSC; 1 = Overlay data bypasses CSC.

GV Select: Selects whether graphics or video data will be passed through the scaler hardware:

0 = Video data; 1 = Graphics data.

3:2

Video Input Format: This field defines the byte ordering of the video data on the VID_DATA bus.

8-Bit Mode (Value Byte Order [0:3])

16-Bit Mode (Value Byte Order [0:3])

00 = U Y0 V Y1 (also used for RGB 5:6:5 input)

01 = Y1 V Y0 U or 4:2:0

01 = Y0 U Y1 V

10 = Y0 U Y1 V

10 = Y1 V Y0 U or 4:2:0

11 = Y0 V Y1 U

11 = Reserved

If bit 28 is enabled, these bits (bits [3:2]) should be set to 01 if in 8-bit video mode and 10 if in 16-bit video mode.

Note: U= Cb, V = Cr

Video Register Update: Allow video position and scale registers to be updated simultaneously on next occurrence of

vertical sync: 0 = Disable; 1 = Enable.

Video Enable: Video acceleration hardware: 0 = Disable; 1 = Enable.

Offset 04h-07h

Display Configuration Register (R/W)

Reset Value = 00000000h

DDC Input Data (Read Only): This is the DDC input data bit for reads.

Red Comparator (Read Only): This is the value of the red video DAC comparator.

Green Comparator (Read Only): This is the value of the green video DAC comparator.

Blue Comparator (Read Only): This is the value of the blue video DAC comparator.

Flat Panel On (Read Only): This bit indicates whether the attached flat panel display is powered on or off. The bit transi-

tions at the end of the power-up or power-down sequence. 0 = Off; 1 = On.

DAC External Voltage Reference Enable: This bit enables the use of an external voltage reference for the video DAC.

When enabled, an external voltage reference should be connected to the EXTVREFIN pin. When disabled, the DAC inter-

nal voltage reference will be used. 0 = Disable; 1 = Enable.

16-Bit Graphics Enable: This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset

00h[29]. This bit should be set to the same value as the 16-bit Video Interface bit.

DDC Output Enable: This bit enables the DDC_SDA line to be driven for write data. 0 = DDC_SDA pin is input;

1 = DDC_SDA pin is output.

DDC Output Data: This is the DDC data bit.

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