CS5530 datasheet(199/241 Pages) NSC

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Video Controller Registers - Function 4

The register space for the video controller is divided into

two sections. The first section is used to configure the PCI

portion of the controller. A Base Address Register at F4

Index 10h (F4BAR) points to the base address of where

the second portion of the register space is located. The

second section contains the registers used by the video

controller to carry out video operations.

Table 4-21 shows the PCI header registers of F4. The

memory mapped registers accessed through F4BAR, and

shown in Table 4-22, must be accessed using DWORD

operations. When writing to one of these 32-bit registers,

all four bytes must be written.

Table 4-21. F4 Index xxh: PCI Header Registers for Video Controller Configuration

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0104h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:2

Reserved (Read Only)

Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable.

This bit must be enabled to access memory offsets through F4BAR (F4 Index 10h).

Reserved (Read Only)

Index 06h-07h

PCI Status Register (RO)

Reset Value = 0280h

Index 08h

Device Revision ID Register (RO)

Reset Value = 00h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 030000h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value = 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value = 00h

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

Index 10h-13h

Base Address Register - F4BAR (R/W)

Reset Value = 00000000h

This register sets the base address of the memory mapped video controller registers. Bits [11:0] are read only (0000 0000 0000), indi-

cating a 4 KB memory address range. Refer to Table 4-22 for the video controller register bit formats and reset values.

31:12

Video Controller and Clock Control Base I/O Address

11:0

Address Range (Read Only)

Index 14h-FFh

Reserved

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