PC87373 datasheet(121/174 Pages) NSC

121 / 174 page

9.0 Glue Functions (Continued)

121

www.national.com

Revision 1.1

Table 46 defines the DC characteristics of the Resume Reset circuit. For the AC characteristics, see Resume Reset on

page 170.

9.2.4

Main Power Good

This function generates the PWRGD_3V signal, indicating that the Main power supply voltage is valid and the reset button

on the front panel is not pressed. The PWRGD_3V signal indicates to system components that their input power supplies

are valid.

The FPRST input is debounced for at least tDB before entering the Main Power Good circuit, to ensure that the signal is

stable. The debouncer adds a tDB delay to the PWRGD_3V output change in output caused by the FPRST input. The de-

bouncer timing is based on the 32 KHz clock domain, which therefore must be valid to enable the correct operation of the

Power Good function.

The PWRGD_3V is the AND function of the PWRGD_PS and FPRST inputs. Figure 26 shows a simplified diagram of the

circuit that generates the PWRGD_3V signal.

Figure 26. PWRGD_3V Generation (Simpliﬁed Diagram)

For the AC characteristics, see Main Power Good on page 171.

9.2.5

Rambus SCK Clock Gate Control

This function generates the SCK_BJT_GATE signal, which controls an external circuit that gates the SCK clock to the Ram-

bus socket.

The SCK clock to the Rambus socket is disabled by an active high SCK_BJT_GATE signal, generated when either the Main

power supply voltage is not valid or the reset button on the front panel is pressed (PWRGD_3V = low).

Figure 27 shows a simplified diagram of the circuit that generates the SCK_BJT_GATE signal.

Figure 27. SCK_BJT_GATE Generation (Simpliﬁed Diagram)

For the AC characteristics, see CNR Downstream Codec Dynamic Control on page 172.

Table 46. Resume Reset Circuit DC Characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

VTRIP

VSB5 Threshold Level

VSB3 = 3.3V ±10%

4.05

4.5

ZOFF

Output Impedance at VSB3 Off

1. Not tested. Guaranteed by characterization.

VSB3 = 0V,

VSB5 =5V ±10%

TBD

Ω

FPRST

Input

Debouncer

PWRGD_PS

PWRGD_3V

1 K

Ω

SCK_BJT_GATE

VSB5

PWRGD_3V

PC87373 数据表(PDF) 121 Page - National Semiconductor (TI)

PC87373 数据表(HTML) 121 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载