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PC87373 数据表(PDF) 140 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87373
功能描述  LPC SuperI/O with Glue Functions
PDF  174 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87373 数据表(HTML) 140 Page - National Semiconductor (TI)

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Revision 1.1
12.0 Legacy Functional Blocks
This chapter briefly describes the following blocks, which provide legacy device functions:
q
Floppy Disk Controller (FDC)
q
Parallel Port (PP)
q
Serial Port1 and 2 (SP1 and SP2)
q
Keyboard and Mouse Controller (KBC)
For details on the general implementation of each legacy block, see the SuperI/O Legacy Functional Blocks datasheet.
The register maps in this chapter use the following abbreviations for Type:
q
R/W
= Read/Write.
q
R
= Read from register (write to the same address is to a different register).
q
W
= Write (see above).
q
RO
= Read Only.
q
WO
= Write Only. Reading from the bit returns 0.
q
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
q
R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.
12.1 FLOPPY DISK CONTROLLER (FDC)
12.1.1 General Description
The generic FDC is a standard FDC with a digital data separator; it is software compatible with the
µDP8473 and N82077.
The PC87373 FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chap-
ter, including:
FDC supportS FM and MFM modes. To select either mode, set bit 6 of the first command byte when writing to/reading
from a diskette, where:
— 0 = FM mode
— 1 = MFM mode
A logic 1 is returned during LPC I/O read cycles by all register bits, reflecting the state of floating (TRI-STATE) FDC pins.
Exceptions to standard FDC are:
Automatic media sense using MSEN0 and MSEN1 signals is not supported.
DRATE1 is not supported.
DR1 is not supported.
MTR1 is not supported.
Table 52 lists the FDC functional block registers. All registers are VDD3 powered.
Table 52. FDC Register Map
Offset1
Mnemonic
Register Name
Type
00h
SRA
Status A
RO
01h
SRB
Status B
RO
02h
DOR
Digital Output
R/W
03h
TDR
Tape Drive
R/W
04h
MSR
Main Status
R
DSR
Data Rate Select
W
05h
FIFO
Data (FIFO)
R/W



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