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PC87373 数据表(PDF) 141 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 141 Page - National Semiconductor (TI) |
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141 / 174 page ![]() 12.0 Legacy Functional Blocks (Continued) 141 www.national.com Revision 1.1 12.1.2 FDC Bitmap Summary The FDC supports two system operation modes: PC-AT mode and PS/2 mode. Unless specifically indicated otherwise, all fields in all registers are valid in both operation modes. 06h N/A X 07h DIR Digital Input R CCR Configuration Control W 1. From the 8-byte aligned FDC base address. Table 53. FDC Bitmap Summary Register Bits Offset Mnemonic 76543210 00h SRA1 1. Applicable only in PS/2 Mode. IRQ Pending Reserved Step TRK0 Head Select INDEX WP Head Direction 01h SRB1 Reserved Drive Select 0 Status WDATA RDATA WGATE MTR1 MTR0 02h DOR Reserved Motor Enable 1 Motor Enable 0 DMAEN Reset Controller Drive Select 03h TDR Reserved Tape Drive Select 1,0 TDR2 2. Applicable only in Enhanced TDR Mode. Reserved (must be 1111) Logical Drive Exchange Tape Drive Select 1,0 04h MSR RQM Data I/O Direction Non-DMA Execution Command in Progress Reserved Drive 1 Busy Drive 0 Busy DSR Software Reset Low Power Reserved Precompensation Delay Select Data Transfer Rate Select 05h FIFO Data Bits 07h DIR3 3. Applicable only in PC-AT Compatible Mode. DSKCHG Reserved DIR1 DSKCHG Reserved DRATE 1,0 Status High Density 07h CCR Reserved DRATE1,0 Table 52. FDC Register Map Offset1 Mnemonic Register Name Type |
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