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PC87373 数据表(PDF) 171 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 171 Page - National Semiconductor (TI) |
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171 / 174 page ![]() 13.0 Device Characteristics (Continued) 171 www.national.com Revision 1.1 Figure 55. RSMRST (AC Characteristics) Main Power Good Rambus SCK Clock Gate Control Power Distribution Control Symbol Figure Description Reference Conditions Min Max Units tDB − Debouncing time1 1. Not tested. Guaranteed by design. After RE or FE of FPRST 768 * tCP 2 2. tCP is the cycle time of the 32 KHz clock domain (see Low-Frequency Clock Timing on page 162) 832 * tCP tPDF − FPRST Propagation Delay1 After RE or FE of FPRST 768 * tCP 832 * tCP tPDP − PWRGD_PS Propagation Delay1 After RE or FE of PWRGD_PS 1 µs tR − Rise Time1 0.8V to 2.0V 50 ns tF − Fall Time1 2.0V to 0.8V 50 ns Symbol Figure Description Reference Conditions Min Max Units tPF − Fall Propagation Delay1 1. Not tested. Guaranteed by characterization. PWRGD_3V to FE of SCK_BJT_GATE 50 ns tF − Fall Time 0.8V to 2.0V 15 ns Symbol Figure Description Reference Conditions Min Max Units tPB − BKFD_CUT Propagation Delay1 1. Not tested. Guaranteed by design. PWRGD_PS or SLP_S3 to BKFD_CUT 1 µs tTB − BKFD_CUT Transition Time1 0.8V to 2.0V 50 ns tPL 56 LATCHED_BF_CUT Propagation Delay1 BKFD_CUT or SLP_S5 to LATCHED_BF_CUT 1 µs tTL 56 LATCHED_BF_CUT Transition Time1 0.8V to 2.0V 50 ns 0.8V tRD tFD3 VSB3 VSB3ON tRD tFD5 RSMRST VSB5 VTRIP tGA VSB3OFF 1.4V tF 2.0V 0.8V 1.4V tR 2.0V 1.4V |
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