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PC87373 数据表(PDF) 173 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 173 Page - National Semiconductor (TI) |
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173 / 174 page ![]() 13.0 Device Characteristics (Continued) 173 www.national.com Revision 1.1 13.4.9 SWC Timing Wake-Up Inputs at VSB3 Power Switching Figure 57. Inputs at VSB3 Power Switching Wake-Up Inputs at VDD3 Power Switching Figure 58. Wake-Up Inputs at VDD3 Power Switching Symbol Figure Description Reference Conditions Min Max tEWIV 57 External Wake-Up Inputs Valid1 1. Not tested. Guaranteed by characterization. At VSB3 power on, after the 32 KHz Domain is toggling 24576 * tCP 2 2. tCP is the cycle time of the 32 KHz clock domain (see Low-Frequency Clock Timing on page 162) 32768 * tCP Symbol Figure Description Reference Conditions Min Max tEWIV 58 External Wake-Up Inputs Valid1 1. Not tested. Guaranteed by characterization. After VDD3 power on 2 2. The 32 KHz clock domain is assumed to be toggling at VDD3 power stable. 24576 * tCP 3 3. tCP is the cycle time of the 32 KHz clock domain (see Low-Frequency Clock Timing on page 162) 32768 * tCP VSB3 (Power) RI GPIOE13-10, tEWIV GPIO07-00, KBCLK, MCLK VSB3OFF VSB3ON KBDAT, MDAT (Internal) VSB Power-Up Reset t32KW + t32KVAL tIRST 32 KHz Domain (Internal) VDD3 (Power) GPIOE13 -10, tEWIV GPIOE07-00 VDD3OFF VDD3ON (VDDLOAD = 1) |
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