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LAN9252/ML 数据表(PDF) 231 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 231 Page - Microchip Technology |
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231 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 231 LAN9252 12.14.9 CONFIGURED STATION REGISTER 12.14.10 CONFIGURED STATION ALIAS REGISTER Note 5: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu- rable Registers," on page 201 for additional information. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.11 WRITE REGISTER ENABLE REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0010h-0011h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Configured Station Address This field contains the address used for node addressing (FPxx commands) R/W RO 0000h Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0012h-0013h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Configured Station Alias Address This field contains the alias address used for node addressing (FPxx commands). The use of this alias is activated by the Sta- tion Alias bit of the ESC DL Control Register. Note: EEPROM value is only taken over at first EEPROM load after lower-on reset. RO R/W 0000h Note 5 Offset: 0020h Size: 8 bits |
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