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LAN9252/ML 数据表(PDF) 258 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 258 Page - Microchip Technology |
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258 / 329 page ![]() LAN9252 DS00001909A-page 258 2015 Microchip Technology Inc. 12.14.42 WATCHDOG TIME PDI REGISTER Note: The watchdog is disabled if Watchdog Time PDI is set to 0000h. Watchdog is restarted with every PDI access. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.43 WATCHDOG TIME PROCESS DATA REGISTER Note: There is one watchdog for all SyncManagers. The watchdog is disabled if Watchdog Time PDI is set to 0000h. The watchdog is restarted with every write access to the SyncManagers with the Watchdog Trigger Enable bit set. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0410h-0411h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Watchdog Time PDI Number of basic watchdog increments. (default value with Watchdog Divider of 100 us results in 100 ms watchdog.) R/W RO 03E8h Offset: 0420h-0421h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Watchdog Time Process Data Number of basic watchdog increments. (default value with Watchdog Divider of 100 us results in 100 ms watchdog.) R/W RO 03E8h |
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