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LAN9252/ML 数据表(PDF) 260 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 260 Page - Microchip Technology |
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260 / 329 page ![]() LAN9252 DS00001909A-page 260 2015 Microchip Technology Inc. 12.14.47 EEPROM CONFIGURATION REGISTER Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Offset: 0500h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:2 RESERVED Write 0. RO RO 000000b 1 Force ECAT Access 0: Do not change 1: Reset R/W RO 0b 0 PDI EEPROM Control 0: No 1: Yes (PDI has EEPROM control) R/W RO 0b |
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