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LAN9252/ML 数据表(PDF) 276 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 276 Page - Microchip Technology

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LAN9252
DS00001909A-page 276
 2015 Microchip Technology Inc.
12.14.60.6 SyncManager x PDI Control Register
12.14.61 RECEIVE TIME PORT 0 REGISTER
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Offset:
SyncManager x Base Address +7h
Size:
8 bits
Bits
Description
ECAT
Type
PDI
Type
Default
7:2
RESERVED
Write as 0.
RO
RO
000000b
1
Repeat Ack
If this is set to the same value as Repeat Request, the PDI
acknowledges the execution of a previous set repeat request.
RO
R/W
0b
0
Deactivate SyncManager x
Read:
0:
Normal operation, SyncManager x activated
1:
SyncManager x deactivated and reset SyncManager x locks
access to memory area
Write:
0:
Activate SyncManager
1:
Request SyncManager Deactivation
RO
R/W
0b
Offset:
0900h-0903h
Size:
32 bits
Bits
Description
ECAT
Type
PDI
Type
Default
31:0
Write:
A write access to register 0900h with BWR, APWR (any
address) or FPWR (configured address) latches the local time of
the beginning of the receive frame (start first bit of preamble) at
each port.
Read:
Local time of the beginning of the last receive frame containing a
write access to this register.
Note:
The time stamps cannot be read in the same frame in
which this register was written.
R/W
RO
Undefined



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