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LAN9252/ML 数据表(PDF) 277 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 277 Page - Microchip Technology |
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277 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 277 LAN9252 12.14.62 RECEIVE TIME PORT 1 REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.63 RECEIVE TIME PORT 2 REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0904h-0907h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 Local time of the beginning of a frame (start first bit of preamble) received at port 1 containing a BWR/APWR or FPWR to the Receive Time Port 0 Register. RO RO Undefined Offset: 0908h-090Bh Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 Local time of the beginning of a frame (start first bit of preamble) received at port 2 containing a BWR/APWR or FPWR to the Receive Time Port 0 Register. RO RO Undefined |
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