PC87373 datasheet(104/174 Pages) NSC

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6.0 System Wake-Up Control (SWC) (Continued)

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Revision 1.1

6.4.11 General-Purpose Enable 1 Register 3 (GPE1_EN_3)

This register contains “child” events 24-31 of the GPE1_EN register.

The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written

by software).

Power Well: VSB3

Location:

Offset 0Fh

Type:

R/W

Bit

76543210

Name

Reserved

MOD_IRQ

_EN

MS_IRQ

_EN

KBD_IRQ

_EN

Reserved

Reset

00000000

Bit

Description

7-5

Reserved.

MOD_IRQ_EN (Modules IRQ Event Enable). Enables an active IRQ from one of the Legacy modules or the

Fan Speed Control and Monitor to set PME_STS bit in GPE1_STS register.

0: Disable event (default)

1: Enable event of an active IRQ from one of the Legacy modules or the Fan Speed Control and Monitor to set

PME_STS

MS_IRQ_EN (Mouse IRQ Event Enable). Enables an IRQ generated by the mouse interface section of the

KBC module to set PME_STS bit in GPE1_STS register.

0: Disable event (default)

1: Enable event of an IRQ generated by the mouse interface section of the KBC module to set PME_STS

KBD_IRQ_EN (Keyboard IRQ Event Enable). Enables an IRQ generated by the keyboard interface section of

the KBC module to set PME_STS bit in GPE1_STS register.

0: Disable event (default)

1: Enable event of an IRQ generated by the keyboard interface section of the KBC module to set PME_STS

1-0

Reserved.

PC87373 数据表(PDF) 104 Page - National Semiconductor (TI)

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