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PC87373 数据表(PDF) 107 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 107 Page - National Semiconductor (TI) |
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107 / 174 page ![]() 107 www.national.com Revision 1.1 7.0 Fan Speed Control This chapter describes a generic Fan Speed Control unit. One or more Fan Speed Control units are included in the Fan Speed Control and Monitor (FSCM) module. For the specific implementation in this device, see Section 3.15.1 on page 67. 7.1 OVERVIEW The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM generator output is used to control the fan power voltage, which is correlated to the fan speed. Converting a 0 to 100% duty cycle PWM signal to an analog voltage range is performed by an external driver circuit, as shown in Figure 17. Some newer fans accept direct PWM input without any external driver. Figure 17. Fan Speed Control - System Configuration 7.2 FUNCTIONAL DESCRIPTION The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale register (FCPSR), used to determine the overall cycle time (or the frequency) of the FANPWM output, and the Fan Speed Control Duty Cycle register (FCDCR), used to determine the duty cycle of the FANPWM between 0 to 100%. The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e., its cycle equals 256 clock periods. The PWM output is high, as long as the count is lower than the FCDCR value and it flips to low as the counter ex- ceeds that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output is continuously low when FCDCR=0; it is continuously high when FCDCR=FFh. The FANOUT output may be inverted by an external configuration bit (FANCTL_INV in FSCMCF1 or FSCMCF2 register; see Section 3.15.3 on page 68 and Section 3.15.4 on page 69), in which case the FANPWM duty cycle is ([256-FCDCR]/256)*100. The PWM counter clock is generated by dividing the input clock (either 24 MHz or 200 KHz), using a clock divider. The di- vision factor, which must be between 1 and 124, is defined as PRE-SCALE +1, where PRE-SCALE is the binary value stored in bits 6 to 0 of the FCPSR register. The resulting PWM output frequency is therefore: (24 MHz or 200 kHz) / ([PRE-SCALE + 1] * 256). The default selection of 24 MHz input clock allows a programmable FANPWM frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input clock allows a frequency range of 6 Hz to 781 Hz (see Figure 18). The FANPWM frequency must be selected, according to the fan type’s specific requirements, prior to enabling the Fan Speed Control. The only register that must be changed at runtime to control the fan speed is the FCDCR register. Warning! The contents of the FCPSR register must not be changed while the Fan Speed Control is enabled. Fan Speed Control Fan FANPWM Control External Driver 24 MHz (1-124) PWM FCDCR Register (FCDCR > Counter) FANPWM FCPSR Register Figure 18. Fan Speed Control - Simplified Diagram O 0 1 200 KHz Bit 7 Bits 6-0 PWM Output - Counter Comparator 0 1 FANCTL_INV Clock Divider CLK_SEL PRE-SCALE DUTY-CYC |
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