PC87373 datasheet(109/174 Pages) NSC

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7.0 Fan Speed Control (Continued)

109

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Revision 1.1

7.3.3

Fan Speed Control Duty-Cycle Register (FCDCR)

This register controls the duty-cycle of the FANPWM signal. It is reset by hardware to FFh.

Power Well: VDD3

Location:

Device specific

Type:

R/W

7.4 FAN SPEED CONTROL REGISTER BITMAP

Bit

43210

Name

DUTY-CYC

Reset

11111

Bit

Description

7-0

DUTY-CYC (Duty-Cycle Value). The binary value of this 8-bit ﬁeld determines the number of clock cycles (out

of a 256-cycle period) during which the PWM output is high (a high FANPWM is either equal to or the inverse

of the PWM output, depending on the FANCTL_INV conﬁguration bit).

00h:

The PWM output is continuously low

01h - FEh: The PWM output is high for [DUTY-CYC] number of clock cycles and low for [256-DUTY-CYC]

number of clock cycles

FFh:

The PWM output is continuously high (default)

Table 41. Fans Speed Control Register Bitmap

Bits

Offset

Mnemonic

76543210

Device Speciﬁc1

1. The location of this register is defined in Section 3.15.1 on page 67.

FCPSR

CLK_SEL

PRE-SCALE

Device Speciﬁc1

FCDCR

DUTY-CYC

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