PC87373 datasheet(113/174 Pages) NSC

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8.0 Fan Speed Monitor (Continued)

113

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Revision 1.1

8.3.3

Fan Speed Monitor Threshold High Register (FMTHRH)

This register holds the high byte (bits 15-8) of the lowest permitted fan speed value. It is reset to FFh.

Power Well: VDD3

Location:

Device specific

Type:

R/W

8.3.4

Fan Speed Monitor Speed Low Register (FMSPRL)

This register contains the low byte (bits 7-0) of the current fan speed value, which is updated once per fan revolution. It is

reset to 00h. Whenever the FMSPRL register is read, the high byte of the FAN_SPD data is latched to save the current fan

speed value until FMSPRH register is read. Therefore, the FMSPRL register must be read ﬁrst. When FMSPRL register is

read, SPD_RDY bit in FMCSR register is reset.

The FAN_SPD data is reset when one of the following conditions occurs:

System reset (see Section 2.2 on page 29).

The corresponding FANMON_EN bit in FSCMCF1 or FSCMCF2 register is reset to 0 (see Section 3.15.3 on page 68

and Section 3.15.4 on page 69).

Power Well: VDD3

Location:

Device specific

Type:

Bit

43210

Name

THRSH_HIGH

Reset

11111

Bit

Description

7-0

THRSH_HIGH (Fan Speed Threshold Value - High). This ﬁeld contains the high byte of the threshold for the

lowest permitted fan speed value; see Section 8.3.2 on page 112 for the description of this ﬁeld.

Bit

43210

Name

FAN_SPD_LOW

Reset

00000

Bit

Description

7-0

FAN_SPD_LOW (Fan Speed Value - Low). This ﬁeld contains the low byte of the current fan speed value. The

16-bit FAN_SPD data represents the number of clock cycles counted during one full revolution of the fan,

according to the setting of TPPR bit in FMCSR register. When SPD_RDY bit is set in FMCSR register,

FAN_SPD contains new speed data that has not yet been read.

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