PC87373 datasheet(110/174 Pages) NSC

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8.0 Fan Speed Monitor (Continued)

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8.0

Fan Speed Monitor

This chapter describes a generic Fan Speed Monitor unit. One or more Fan Speed Monitor units are included in the Fan

Speed Control and Monitor (FSCM) module. For the implementation used in this device, see Section 3.15.1 on page 67.

8.1 OVERVIEW

The Fan Speed Monitor measures the fan speed by measuring the time between consecutive “active” tachometer pulses

(obtained from the tachometer pulses generated by the fan). The FSM provides to the system a current speed reading; it

can also alert the system by interrupt whenever the speed drops below a programmable threshold. The FSM indicates

whether the speed is just below the threshold or low enough to consider the fan stopped (i.e., inefficient fan operation).

Figure 19 shows the basic system configuration of the Fan Speed Monitor.

Figure 19. Fan Speed Monitor - System Conﬁguration

8.2 FUNCTIONAL DESCRIPTION

The fan generates a tachometer pulse every half or full revolution (depending on the fan type). These pulses are fed into the

Fan Speed Monitor through the FANTACH input pin.

The FANTACH pin has a Schmitt Trigger input buffer. In addition, the FANTACH signal passes through a digital filter, which

ignores any tachometer pulses shorter than 750

µs. This filter can be enabled by setting FILTER_DIS bit in FMCSR register

to 0.

Speed monitoring is based on measuring the time between tachometer pulses generated by the fan. The Fan Speed Monitor

measures the time for a full fan revolution. Since fans generate one or two tachometer pulses per revolution (depending on

the fan type), the incoming pulses at the FANTACH pin are either used directly or are divided by 2 to produce the active

tachometer pulses. These active pulses eventually control the fan speed counter. Incoming tachometer pulse decimation is

controlled by TPPR bit in FMCSR register.

The fan speed measured by the counter during a full fan revolution is stored as a 16-bit FAN_SPD value, where

FAN_SPD_HIGH is the high byte and FAN_SPD_LOW is the low byte. The rotational speed of the fan is calculated accord-

ing to the following relationship:

Rotational Speed of Fan (in RPM) =

The Fan Speed Monitor consists of a 16-bit counter, which measures the fan speed, and two 16-bit registers, FAN_SPD,

which holds the current fan speed value, and THRSH, which holds the threshold value. The 16-bit THRSH value is com-

posed of THRSH_HIGH (the high byte) and THRSH_LOW (the low byte). Figure 20 is a simplified diagram of the Fan Speed

Monitor.

The Up Counter and the FAN_SPD data are cleared to 0 when the Fan Speed Monitor is disabled.

When the Fan Speed Monitor is enabled (by FANMON_EN bit in FSCMCF1 or FSCMCF2 register; see Section 3.15.3 on

page 68 and Section 3.15.4 on page 69) and there is no counter overﬂow, the Up Counter, which is clocked by a 32.000

KHz internal clock, increments by 1. Starting from the second active FANTACH pulse (after activation) and on every subse-

quent active FANTACH pulse, the FAN_SPD data is updated with the contents of the counter, the counter is cleared to 0

and SPD_RDY bit in FMCSR register is set to 1.

The above operation continually repeats itself, updating the current speed value as long as the FAN_SPD value is less than

or equal to the THRSH value.

When the FAN_SPD value exceeds the THRSH value, OVR_THR bit in FMCSR register is set to 1. An interrupt is also as-

serted if IRQ_EN bit in FMCSR register is set to 1 (i.e., interrupt is enabled). After OVR_THR bit is set, the FAN_SPD data

is no longer updated with new values from the Up Counter. A new value is loaded into FAN_SPD data only after OVR_THR

bit is cleared by writing 1. This guarantees that the FAN_SPD value that generated the interrupt remains available for the

interrupt handler.

If the Up Counter exceeds FFFFh, OVFLOW bit in FMCSR register is set to 1, the FAN_SPD data is set to FFFFh, and the

interrupt is asserted (if enabled). The FAN_SPD data continues to be updated with new values from the Up Counter.

OVFLOW bit is cleared to 0 when 1 is written to it.

Fan Speed

FANTACH

Fan

Tachometer Pulse

Filtering

Circuit

Monitor

(optional)

60 *

32000

FAN_SPD

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