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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PC87373 数据表(PDF) 112 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 112 Page - National Semiconductor (TI) |
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112 / 174 page  8.0 Fan Speed Monitor (Continued) 112 www.national.com Revision 1.1 8.3 FAN SPEED MONITOR REGISTERS The following abbreviations are used to indicate the Register Type: q R/W = Read/Write. q R = Read from register (write to the same address is to a different register). q W = Write (see above). q RO = Read Only. q WO = Write Only. Reading from the bit returns 0. q R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. q R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 8.3.1 Fan Speed Monitor Register Map 8.3.2 Fan Speed Monitor Threshold Low Register (FMTHRL) This register holds the low byte (bits 7-0) of the lowest permitted fan speed value. It is reset to FFh. Power Well: VDD3 Location: Device specific Type: R/W Table 42. Fan Speed Monitor Register Map Offset Mnemonic Register Name Type Power Well Section Device specific1 1. The location of this register is defined in Section 3.15.1 on page 67. FMTHRL Fan Speed Monitor Threshold Low R/W VDD3 8.3.2 Device specific1 FMTHRH Fan Speed Monitor Threshold High R/W VDD3 8.3.3 Device specific1 FMSPRL Fan Speed Monitor Speed Low RO VDD3 8.3.4 Device specific1 FMSPRH Fan Speed Monitor Speed High RO VDD3 8.3.5 Device specific1 FMCSR Fan Speed Monitor Control and Status Varies per bit VDD3 8.3.6 Bit 76 5 43210 Name THRSH_LOW Reset 1 1 1 11111 Bit Description 7-0 THRSH_LOW (Fan Speed Threshold Value - Low). This field contains the low byte of the threshold setting, indicating the lowest permitted fan speed value. If the number of clock cycles counted in one fan revolution is higher than the THRSH value, OVR_THR bit is set in FMCSR register and the FAN_SPD data is “frozen” at its last value. In addition, an interrupt (if enabled) is issued. To prevent unpredictable results, the contents of this register can only be changed when the corresponding FANMON_EN bit in FSCMCF1 or FSCMCF2 register is reset to 0 (see Section 3.15.3 on page 68 and Section 3.15.4 on page 69). |
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