PC87373 datasheet(114/174 Pages) NSC

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8.0 Fan Speed Monitor (Continued)

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Revision 1.1

8.3.5

Fan Speed Monitor Speed High Register (FMSPRH)

This register contains the high byte (bits 15-8) of the current fan speed value, which is updated once per fan revolution. It is

reset to 00h. FMSPRH register must be read last; see Section 8.3.4 on page 113.

Power Well: VDD3

Location:

Device specific

Type:

8.3.6

Fan Speed Monitor Control and Status Register (FMCSR)

This register contains control and status bits of the Fan Speed Monitor unit. FMCSR is reset to 10h.

Power Well: VDD3

Location:

Device specific

Type:

Varies per bit

Bit

43210

Name

FAN_SPD_HIGH

Reset

00000

Bit

Description

7-0

FAN_SPD_HIGH (Fan Speed Value - High). This ﬁeld contains the high byte of the current fan speed value.

See Section 8.3.4 on page 113 for the description of this ﬁeld.

Bit

76543210

Name

TPPR

Reserved

FILTER_DIS

IRQ_EN

OVFLOW

OVR_THR

SPD_RDY

Reset

00010000

Bit

Type

Description

R/W

TPPR (Tachometer Pulses Per Revolution). This bit selects the number of pulses per fan revolution

generated by the tachometer and thus the division factor of the incoming pulses at the FANTACH pin.

0: Two pulses per revolution: division by 2 (default)

1: One pulse per revolution: no division

To prevent unpredictable results, the value of this bit can only be changed when the corresponding

FANMON_EN bit in FSCMCF1 or FSCMCF2 register is reset to 0 (see Section 3.15.3 on page 68 and Sec-

tion 3.15.4 on page 69).

6-5

–

Reserved.

R/W

FILTER_DIS (Filter Disable). When this bit is set to 1, the digital Low Pass Filter on the FANTACH

input is disabled.

0: Digital Low Pass Filter enabled

1: Digital Low Pass Filter disabled (default)

To prevent unpredictable results, the value of this bit can only be changed when the corresponding

FANMON_EN bit in FSCMCF1 or FSCMCF2 register is reset to 0 (see Section 3.15.3 on page 68 and Sec-

tion 3.15.4 on page 69).

R/W

IRQ_EN (Fan Interrupt Enable). This bit controls the routing of Overﬂow and Over Threshold events to

the FSCM module interrupt.

0: Interrupt disabled (default)

1: Interrupt enabled. An interrupt is asserted when either OVR_THR bit or OVFLOW bit is set to 1.

R/W1C OVFLOW (Overflow). This bit indicates that the number of clock cycles counted during one full

revolution of the fan exceeds 65536 (FFFFh) clocks. This is equivalent to a fan speed slower than

29.3 RPM. At this speed, fan cooling is inefﬁcient; therefore, the fan is considered stopped and an

interrupt (if enabled) is issued. Writing 1 to this bit clears it to 0.

0: No overﬂow occurred since the last time this bit was cleared by writing 1 (default)

1: Counter overﬂow (FFFFh) occurred

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