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PC87373 数据表(PDF) 165 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 165 Page - National Semiconductor (TI) |
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165 / 174 page  13.0 Device Characteristics (Continued) 165 www.national.com Revision 1.1 13.4.5 FDC Timing FDC Write Data Timing tDRP tICP tWDW Values Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactive1 1. Not tested. Guaranteed by design. 100 µs tHDS HDSEL Setup to WGATE Active1 100 µs tWDW Write Data Pulse Width1 See tDRP,tICP and tWDW values in table below Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit 1 Mbps 1000 6xtCP 1 1. tCP is the clock period defined for CLOCKI in Clock Timing on page 161. 125 2 x tICP 250 ns 500 Kbps 2000 6xtCP 1 125 2 x tICP 250 ns 300 Kbps 3333 10 x tCP 1 208 2 x tICP 375 ns 250 Kbps 4000 12 x tCP 1 250 2 x tICP 500 ns 2.0V 1.4V tF 0.8V 2.0V Reset Outputs VDD3 = 3.3V ±10% tPDF PCI_RESET PCIRST_OUT2 IDE_RSTDRV PCIRST_OUT, tPDR 1.4V tR 0.8V tHDS tHDH tWDW HDSEL WGATE WDATA |
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