LAN9252SLASHML datasheet(222/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 222

 2015 Microchip Technology Inc.

12.13.8

ETHERCAT PROCESS RAM WRITE COMMAND REGISTER (ECAT_PRAM_WR_CMD)

This read/write register is used in conjunction with the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_-

DATA) and the EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) to per-

form write operations to the EtherCAT Core Process RAM.

Offset:

314h

Size:

32 bits

Bits

Description

Type

Default

PRAM Write Busy (PRAM_WRITE_BUSY)

When a 1 is written to this bit, the write operation is started beginning at the

EtherCAT Core Process RAM location specified in PRAM Write Address

(PRAM_WRITE_ADDR) for the length specified in PRAM Write Length

(PRAM_WRITE_LEN). This bit will remain set until the entire write operation

is complete, at which time the bit will self-clear.

Writing a 0 to this bit has no affect.

R/W

PRAM Write Abort (PRAM_WRITE_ABORT)

Writing a 1 to this bit will cause the write operation in process to be canceled.

The PRAM Write Busy (PRAM_WRITE_BUSY) will be cleared and the Write

Data FIFO, along with the status bits, will be reset. This bit will self-clear.

Writing a 0 to this bit has no affect.

R/W

29:13

RESERVED

12:8

PRAM Write Space Available Count (PRAM_WRITE_AVAIL_CNT)

This field indicates the number of times that the EtherCAT Process RAM

Write Data FIFO (ECAT_PRAM_WR_DATA) can be written without further

need to check the status.

This field is decremented when the a entire DWORD of data is written into

the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA).

This field increments as data is read from the FIFO and placed into the Ether-

CAT Core.

10000b

7:1

RESERVED

PRAM Write Space Available (PRAM_WRITE_AVAIL)

This field indicates that the EtherCAT Process RAM Write Data FIFO

(ECAT_PRAM_WR_DATA) has available space for data to be written.

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