LAN9252SLASHML datasheet(218/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 218

 2015 Microchip Technology Inc.

12.13.4

ETHERCAT CSR INTERFACE COMMAND REGISTER (ECAT_CSR_CMD)

This read/write register is used in conjunction with the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) to

perform read and write operations with the EtherCAT Core CSRs.

Note 4:

WORD and DWORD accesses must be aligned on the proper address boundary according to the following

table.

Offset:

304h

Size:

32 bits

Bits

Description

Type

Default

CSR Busy (CSR_BUSY)

When a 1 is written to this bit, the read or write operation (as determined by

the R_nW bit) is performed to the specified EtherCAT Core CSR in CSR

Address (CSR_ADDR).

This bit will remain set until the operation is complete, at which time the bit

will self-clear. In the case of a read, the clearing of this bit indicates to the

Host that valid data can be read from the EtherCAT CSR Interface Data Reg-

ister (ECAT_CSR_DATA).

Writing a 0 to this bit has no affect.

The host should not modify the ETHERCAT_CSR_CMD and ETHER-

CAT_CSR_DATA registers unless this bit is a 0.

R/W

Read/Write (R_nW)

This bit determines whether a read or write operation is performed by the

Host to the specified EtherCAT Core CSR.

0: Write

1: Read

R/W

29:19

RESERVED

18:16

CSR Size (CSR_SIZE)

This field specifies the size of the EtherCAT Core CSR in bytes.

Valid values are 1, 2 and 4. The host should not use invalid values. Note 4.

R/W

15:0

CSR Address (CSR_ADDR)

This field selects the EtherCAT Core CSR that will be accessed with a read

or write operation. This is a byte address which is the format used to specify

the offsets of the EtherCAT Core CSRs.

Note 4.

R/W

00h

TABLE 12-14: ETHERCAT CSR ADDRESS VS. SIZE

CSR_SIZE[2:0]

CSR_ADDR[1:0]

00b, 01b, 10b, 11b

00b, 10b

400b

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