LAN9252SLASHML datasheet(216/329 Pages) MICROCHIP

部件名	LAN9252/ML

功能描述	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

Scroll/Zoom	100%

制造商	MICROCHIP [Microchip Technology]

网页	http://www.microchip.com

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216 / 329 page

LAN9252

DS00001909A-page 216

 2015 Microchip Technology Inc.

12.13.2

ETHERCAT PROCESS RAM WRITE DATA FIFO (ECAT_PRAM_WR_DATA)

This write only register is used in conjunction with the EtherCAT Process RAM Write Command Register

(ECAT_PRAM_WR_CMD)

and

the

EtherCAT

Process

RAM

Write

Address

and

Length

(ECAT_PRAM_WR_ADDR_LEN) to perform write operations to the EtherCAT Core Process RAM.

The host should not write this register unless there is available space as indicated by the PRAM Write Space Available

(PRAM_WRITE_AVAIL) bit in the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD).

Offset:

020h-03Ch

Size:

32 bits

Bits

Description

Type

Default

31:0

EtherCAT Process RAM Write Data (PRAM_WR_DATA)

This field contains the value written to the EtherCAT Core Process RAM.

Note:

Some bytes maybe invalid based on the starting address and

transfer length.

LAN9252/ML 数据表(PDF) 216 Page - Microchip Technology