LAN9252SLASHML datasheet(220/329 Pages) MICROCHIP

220 / 329 page

LAN9252

DS00001909A-page 220

 2015 Microchip Technology Inc.

12.13.6

ETHERCAT PROCESS RAM READ COMMAND REGISTER (ECAT_PRAM_RD_CMD)

This read/write register is used in conjunction with the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_-

DATA) and the EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) to per-

form read operations from the EtherCAT Core Process RAM.

Offset:

30Ch

Size:

32 bits

Bits

Description

Type

Default

PRAM Read Busy (PRAM_READ_BUSY)

When a 1 is written to this bit, the read operation is started beginning at the

EtherCAT Core Process RAM location specified in PRAM Read Address

(PRAM_READ_ADDR) for the length specified in PRAM Read Length

(PRAM_READ_LEN). This bit will remain set until the entire read operation is

complete, at which time the bit will self-clear.

Writing a 0 to this bit has no affect.

R/W

PRAM Read Abort (PRAM_READ_ABORT)

Writing a 1 to this bit will cause the read operation in process to be canceled.

The PRAM Read Busy (PRAM_READ_BUSY) will be cleared and the Read

Data FIFO, along with the status bits, will be reset. This bit will self-clear.

Writing a 0 to this bit has no affect.

R/W

29:13

RESERVED

12:8

PRAM Read Data Available Count (PRAM_READ_AVAIL_CNT)

This field indicates the number of times that the EtherCAT Process RAM

Read Data FIFO (ECAT_PRAM_RD_DATA) can be read without further need

to check the status.

This field increments as data is read from the EtherCAT Core and placed into

the FIFO. This field is decremented when the a entire DWORD of data is

read from the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_-

DATA).

00000b

7:1

RESERVED

PRAM Read Data Available (PRAM_READ_AVAIL)

This field indicates that the EtherCAT Process RAM Read Data FIFO

(ECAT_PRAM_RD_DATA) has valid data to be read.

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