LAN9252SLASHML datasheet(212/329 Pages) MICROCHIP

212 / 329 page

LAN9252

DS00001909A-page 212

 2015 Microchip Technology Inc.

If the initial length is 4 bytes of less and all bytes fit into one read, the valid bytes in the only FIFO read are as follows:

12.11.3.1

Aborting a Read

If necessary, a read command can be aborted by setting the PRAM Read Abort (PRAM_READ_ABORT) bit in the Eth-

erCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD).

12.11.4

ETHERCAT PROCESS RAM WRITES

Process data is transferred to the EtherCAT Core through a 16 deep 32-bit wide FIFO. The FIFO has the base address

of 20h, however, it is also accessible at seven additional contiguous memory locations. The Host may access the FIFO

at any of these alias port locations, as they all function identically and contain the same data. This alias port addressing

is implemented to allow hosts to burst through sequential addresses.

For HBI access, the Process RAM Write Data FIFO may also be accessed using FIFO Direct Selection mode. In this

mode, the address input is ignored and all write accesses are directed to the Process RAM Write Data FIFO. See Sec-

tion 9.4.3.1, "FIFO Direct Select Access," on page 68.

To perform a write to the EtherCAT Process RAM, the write cycle is initiated by first writing the EtherCAT Process RAM

Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) with the starting byte address and length (in

bytes) of the desired transfer followed by a write to the EtherCAT Process RAM Write Command Register

(ECAT_PRAM_WR_CMD) with the PRAM Write Busy (PRAM_WRITE_BUSY) bit set.

Data is transferred into the EtherCAT Core through a 16 deep 32-bit wide FIFO. The host may write data to the FIFO

through the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) when space is available as indicated

by the PRAM Write Space Available (PRAM_WRITE_AVAIL) bit in the EtherCAT Process RAM Write Command Regis-

ter (ECAT_PRAM_WR_CMD). The PRAM Write Space Available Count (PRAM_WRITE_AVAIL_CNT) field indicates

how many writes can be performed without needing to check the status again. Following the final write of the data into

the EtherCAT Core, the PRAM Write Busy (PRAM_WRITE_BUSY) self-clears.

As the data is transferred to the EtherCAT Core from the FIFO the PRAM Write Length (PRAM_WRITE_LEN) and

PRAM Write Address (PRAM_WRITE_ADDR) are updated to show the progress.

Based on the starting address, the valid bytes in the first FIFO write are as follows:

TABLE 12-9:

ETHERCAT PROCESS RAM VALID BYTES ONE READ

Starting Length

Starting

Address[1:0]

4123

00b

bytes 3, 2, 1 and 0

byte 0

bytes 1 and 0

bytes 2, 1 and 0

01b

byte 1

bytes 2 and 1

bytes 3, 2 and 1

10b

byte 2

bytes 3 and 2

11b

nabyte 3na

Note:

The starting byte address and length must be programmed with valid values such that all transfers are

within the bounds of the Process RAM address range of 1000h to 1FFFh.

Note:

The final write of the EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA) implies that all

four bytes have been written, even if not all bytes are required.

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