LAN9252SLASHML datasheet(209/329 Pages) MICROCHIP

209 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 209

LAN9252

The EtherCAT Core Process Data RAM can be accessed indirectly via the EtherCAT CSR Interface Data Register

(ECAT_CSR_DATA) and EtherCAT CSR Interface Command Register (ECAT_CSR_CMD), starting at 1000h. The Eth-

erCAT Core Process Data RAM can also be accessed more efficiently using the EtherCAT Process RAM Read Data

FIFO (ECAT_PRAM_RD_DATA) and EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA). This

method provides for multiple DWORDS to be transferred via a FIFO mechanism using a single command and fewer

status reads.

12.11.1

ETHERCAT CSR READS

To perform a read of an individual EtherCAT Core register, the read cycle must be initiated by performing a single write

to the EtherCAT CSR Interface Command Register (ECAT_CSR_CMD) with the CSR Busy (CSR_BUSY) bit set, the

CSR Address (CSR_ADDR) field set to the desired register address, the Read/Write (R_nW) bit set and the CSR Size

(CSR_SIZE) field set to the desired size.

Valid data is available for reading when the CSR Busy (CSR_BUSY) bit is cleared, indicating that the data can be read

from the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA).

Valid data is always aligned into the lowest bits of the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA).

Figure 12-10 illustrates the process required to perform a EtherCAT Core CSR read. Minimum wait periods are required

where noted. The minimum wait periods as specified in Table 5-2, “Read After Write Timing Rules,” on page 35 are

required where noted.

Note:

All bytes of the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) are updated regardless of the

value of CSR Size (CSR_SIZE).

FIGURE 12-10:

ETHERCAT CSR READ ACCESS FLOW DIAGRAM

Idle

Write

Command

Read

Command

Read Data

CSR_ BUSY =0

CSR Read

CSR_ BUSY = 1

min wait period

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