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LAN9252/ML 数据表(PDF) 144 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 144 Page - Microchip Technology |
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144 / 329 page  LAN9252 DS00001909A-page 144 2015 Microchip Technology Inc. 11.2.16.1 PHY x Basic Control Register (PHY_BASIC_CONTROL_x) This read/write register is used to configure the PHY. Index (decimal): 0 Size: 16 bits Bits Description Type Default 15 Soft Reset (PHY_SRST) When set, this bit resets all the PHY registers to their default state, except those marked as NASR type. This bit is self clearing. 0: Normal operation 1: Reset R/W SC 0b 14 Loopback (PHY_LOOPBACK) This bit enables/disables the loopback mode. When enabled, transmissions are not sent to network. Instead, they are looped back into the PHY. 0: Loopback mode disabled (normal operation) 1: Loopback mode enabled R/W 0b 13 Speed Select LSB (PHY_SPEED_SEL_LSB) This bit is used to set the speed of the PHY when the Auto-Negotiation Enable (PHY_AN) bit is disabled. 0: 10 Mbps 1: 100 Mbps R/W 1b 12 Auto-Negotiation Enable (PHY_AN) This bit enables/disables Auto-Negotiation. When enabled, the Speed Select LSB (PHY_SPEED_SEL_LSB) and Duplex Mode (PHY_DUPLEX) bits are overridden. This bit is forced to a 0 if the 100BASE-FX Mode (FX_MODE) bit of the PHY x Special Modes Register (PHY_SPECIAL_MODES_x) is a high. 0: Auto-Negotiation disabled 1: Auto-Negotiation enabled R/W Note 6 11 Power Down (PHY_PWR_DWN) This bit controls the power down mode of the PHY. 0: Normal operation 1: General power down mode R/W 0b 10 RESERVED RO - 9 Restart Auto-Negotiation (PHY_RST_AN) When set, this bit restarts the Auto-Negotiation process. 0: Normal operation 1: Auto-Negotiation restarted R/W SC 0b |
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