PC87373 datasheet(156/174 Pages) NSC

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13.0 Device Characteristics (Continued)

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Revision 1.1

13.2.11

Input/Output Switch, SMBus Compatible

Symbol: SWSM

13.2.12

Exceptions

1. All pins are 5V tolerant except for the pins with PCI (INPCI, OPCI) buffer types.

2. All pins are back-drive protected except for the output pins with PCI (OPCI) buffer types.

3. The following pins are excluded from the requirement of total pins leakage maximum 10

µA: V

SB5, REF5V,

REF5V_STBY, 3V_DDCSCL, 5V_DDCSCL, 3V_DDCSDA, 5V_DDCSDA, SMB1_SCL, SMB1_SDA, SMB2_SCL,

SMB2_SDA.

4. The following pins have an internal static pull-up resistor (when enabled) and therefore may have leakage current from

VSUP (when VIN = 0): LPCPD, ACK, AFD_DSTRB, ERR, INIT, PE, SLIN_ASTRB, STB_WRITE, KBRST, GA20, SIOPME,

JYABT0-1, JYBBT0-1, MDRX, GPIOE00-07, GPIOE10-13, PWRGD_PS, CPU_PRESENT, FPRST, PRIMARY_HD,

SECONDARY_HD, SCSI.

5. The following pins have an internal static pull-down resistor (when enabled) and therefore may have leakage current to

VSS (when VIN = VSUP): BUSY_WAIT, PE and SLCT.

6. The following strap pins have an internal static pull-up resistor enabled during Power-Up reset and therefore may have

leakage current to VSUP (when VIN = 0): BADDR, TRIS, TEST.

7. When VDD3 = 0V, the following pins present a DC load to VSS of 30 KΩ minimum (not tested, guaranteed by design) for

a pin voltage of 0V to 3.6V: CTS1, CTS2, DCD1, DCD2, DSR1, DSR2, DTR_BOUT1, DTR_BOUT2, RI1, RI2, RTS1,

RTS2, SIN1, SIN2, SOUT1, SOUT2.

8. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 register is 0) is open-drain in all SPP modes except in

SPP-Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1.

Otherwise, output from these signals is level 2. External 4.7 K

Ω pull-up resistors should be used.

9. Output from ACK, ERR (and PE if bit 2 of PP Confg0 register is set to 1) is open-drain in all SPP modes except in SPP-

Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1.

Otherwise, output from these signals is level 2. External 4.7 K

Ω pull-up resistors should be used.

10. Output from STB, AFD, INIT and SLIN is open-drain in all SPP modes, except in SPP-Compatible mode when the setup

mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 K

Ω pull-up resistors should be

used.

11. IOH is valid for a GPIO pin only when it is not configured as open-drain.

12. In XOR Tree mode, the buffer type of the input pins participating in the XOR Tree (see Section 2.4.2 on page 33) is INT

(Input, TTL compatible), regardless of the buffer type of these pins in normal device operation mode (see Section 1.4 on

page 16)

13.2.13

Terminology

Back-Drive Protection. A pin that is back-drive protected does not sink current into the supply when an input voltage higher

than the supply, but below the pin’s maximum input voltage, is applied to the pin. This is true even when the supply is inac-

tive. Note that active pull-up resistors and active output buffers are typically not back-drive protected.

5-Volt Tolerance. An input signal that is 5V tolerant can operate with input voltage of up to 5V even though the supply to

the device is only 3.3V. The actual maximum input voltage allowed to be supplied to the pin is indicated by the maximum

high voltage allowed for the input buffer. Note that some pins have multiple buffers, not all of which are 5V tolerant. In such

cases, there is a note that indicates at what conditions a 5V input may be applied to the pin; if there is no note, the low max-

imum voltage among the buffers is the maximum voltage allowed for the pin.

Symbol

Parameter

Conditions

Min

Max

Unit

VDRP

Pin-to-Pin Voltage Drop

ISW = ±3 mA, Switch Closed

1501

1. Not tested. Guaranteed by characterization.

VISC

Input Voltage for Switch Closed

ISW = ±3mA

1.51

VISO

Input Voltage for Switch Open

ISW = ±20 µA

VSUP

2,3

2. VSUP is VDD3 or VSB3 according to the pin power well.

3. Not tested. Guaranteed by design.

IIL

Input Leakage Current

VISO <VIN < 5.5V

±201

µA

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