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PC87373 数据表(PDF) 160 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 160 Page - National Semiconductor (TI) |
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160 / 174 page ![]() 13.0 Device Characteristics (Continued) 160 www.national.com Revision 1.1 VDD Power-Up Reset Figure 49. Internal VDD Power-Up Reset Hardware Reset Figure 50. Hardware Reset Symbol Figure Description Reference Conditions Min1 1. Not tested. Guaranteed by design. Max1 tIRST 49 Internal Power-Up reset time VDD3 power-up to end of internal reset tLRST tLRST 49 PCI_RESET active time VDD3 power-up to end of PCI_RESET 10 ms tIPLV 49 Internal strap pull-up resistor, valid time2 2. Active only during VDD3 Power-Up reset. Before end of internal reset tIRST tEPLV 49 External strap pull-down resistor, valid time Before end of internal reset tIRST Symbol Figure Description Reference Conditions Min Max tWRST 50 PCI_RESET pulse width 100 ns Internal Straps tIPLV tEPLV (Pull-up) (Pull-Down) External Straps VDD3 (Power) (Internal) PCI_RESET VDD Power-Up Reset tIRST VDDONmin tLRST Internal Clock PCI_RESET tWRST |
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