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LAN9252/ML 数据表(PDF) 157 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 157 Page - Microchip Technology |
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157 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 157 LAN9252 11.2.16.10 PHY x MMD Access Control Register (PHY_MMD_ACCESS) This register in conjunction with the PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA) provides indirect access to the MDIO Manageable Device (MMD) registers. Refer to the MDIO Manageable Device (MMD) Reg- isters on page 175 for additional details. Index (In Decimal): 13 Size: 16 bits Bits Description Type Default 15:14 MMD Function This field is used to select the desired MMD function: 00 = Address 01 = Data, no post increment 10 = RESERVED 11 = RESERVED R/W 00b 13:5 RESERVED RO - 4:0 MMD Device Address (DEVAD) This field is used to select the desired MMD device address. (3 = PCS, 7 = auto-negotiation) R/W 0h |
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