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LAN9252/ML 数据表(PDF) 161 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 161 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 161
LAN9252
11.2.16.13 PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
This read/write register is used to control and monitor various PHY configuration options.
Note 8:
Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
Index (decimal): 17
Size:
16 bits
Bits
Description
Type
Default
15:14
RESERVED
RO
-
13
Energy Detect Power-Down (EDPWRDOWN)
This bit controls the Energy Detect Power-Down mode.
0: Energy Detect Power-Down is disabled
1: Energy Detect Power-Down is enabled
Note:
When in EDPD mode, the device’s NLP characteristics can be
modified via the PHY x EDPD NLP / Crossover Time / EEE
Configuration Register (PHY_EDPD_CFG_x).
R/W
0b
12:7
RESERVED
RO
-
6
ALTINT
Alternate Interrupt Mode:
0 = Primary interrupt system enabled (Default)
1 = Alternate interrupt system enabled
Refer to Section 11.2.7, "PHY Interrupts," on page 128 for additional informa-
tion.
R/W
NASR
Note 8
0b
5:2
RESERVED
RO
-
1
Energy On (ENERGYON)
Indicates whether energy is detected. This bit transitions to “0” if no valid
energy is detected within 256 ms (1500 ms if auto-negotiation is enabled). It
is reset to “1” by a hardware reset and by a software reset if auto-negotiation
was enabled or will be enabled via strapping. Refer to Section 11.2.8.2,
"Energy Detect Power-Down," on page 131 for additional information.
RO
1b
0
RESERVED
RO
-



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