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LAN9252/ML 数据表(PDF) 164 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 164 Page - Microchip Technology |
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164 / 329 page  LAN9252 DS00001909A-page 164 2015 Microchip Technology Inc. 11.2.16.15 PHY x TDR Patterns/Delay Control Register (PHY_TDR_PAT_DELAY_x) Note 13: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg- ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. Index (In Decimal): 24 Size: 16 bits Bits Description Type Default 15 TDR Delay In 0 = Line break time is 2 ms. 1 = The device uses TDR Line Break Counter to increase the line break time before starting TDR. R/W NASR Note 13 1b 14:12 TDR Line Break Counter When TDR Delay In is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds. R/W NASR Note 13 001b 11:6 TDR Pattern High This field specifies the data pattern sent in TDR mode for the high cycle. R/W NASR Note 13 101110b 5:0 TDR Pattern Low This field specifies the data pattern sent in TDR mode for the low cycle. R/W NASR Note 13 011101b |
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