LAN9252SLASHML datasheet(162/329 Pages) MICROCHIP

162 / 329 page

LAN9252

DS00001909A-page 162

 2015 Microchip Technology Inc.

11.2.16.14 PHY x Special Modes Register (PHY_SPECIAL_MODES_x)

This read/write register is used to control the special modes of the PHY.

Note 9:

ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the

PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.

Note 10:

The default value of this bit is determined by the Fiber Enable strap (fx_mode_strap_1 for PHY A, fx_-

mode_strap_2 for PHY B).

Note 11:

This field defaults to 100b when in 100BASE-TX mode (since EtherCAT only uses Auto-Negotiate, 100

Mbps, Full-Duplex) or to 011b when in 100BASE-FX mode (since EtherCAT only uses 100 Mbps, Full-

Duplex).

Note 12:

The default value of this field is determined per Section 11.1.1, "PHY Addressing," on page 120.

Index (decimal): 18

Size:

16 bits

Bits

Description

Type

Default

15:11

RESERVED

100BASE-FX Mode (FX_MODE)

This bit enables 100BASE-FX Mode

Note:

FX_MODE cannot properly be changed with this bit. This bit must

always be written with its current value. Device strapping must be

used to set the desired mode.

R/W

NASR

Note 9

Note 10

9:8

RESERVED

7:5

PHY Mode (MODE[2:0])

This field controls the PHY mode of operation. Refer to Table 11-12 for a defi-

nition of each mode.

Note:

This field should be written with its read value.

R/W

NASR

Note 9

Note 11

4:0

PHY Address (PHYADD)

The PHY Address field determines the MMI address to which the PHY will

respond and is also used for initialization of the cipher (scrambler) key. Each

PHY must have a unique address. Refer to Section 11.1.1, "PHY Address-

ing," on page 120 for additional information.

Note:

No check is performed to ensure that this address is unique from

the other PHY addresses (PHY A, PHY B).

R/W

NASR

Note 9

Note 12

TABLE 11-12: MODE[2:0] DEFINITIONS

MODE[2:0]

Mode Definitions

000

10BASE-T Half Duplex. Auto-Negotiation disabled.

001

10BASE-T Full Duplex. Auto-Negotiation disabled.

010

100BASE-TX or 100BASE-FX Half Duplex. Auto-Negotiation disabled. CRS is active

during Transmit & Receive.

011

100BASE-TX or 100BASE-FX Full Duplex. Auto-Negotiation disabled. CRS is active

during Receive.

LAN9252/ML 数据表(PDF) 162 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 162 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

LAN9252/ML 数据表(PDF) 162 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 162 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载