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LAN9252/ML 数据表(PDF) 160 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 160 Page - Microchip Technology |
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160 / 329 page  LAN9252 DS00001909A-page 160 2015 Microchip Technology Inc. Note 7: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg- ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. 2 RESERVED RO - 1 EDPD Extend Crossover When in Energy Detect Power-Down (EDPD) mode (Energy Detect Power- Down (EDPWRDOWN) = 1), setting this bit to 1 extends the crossover time by 2976 ms. 0 = Crossover time extension disabled 1 = Crossover time extension enabled (2976 ms) R/W NASR Note 7 0b 0 Extend Manual 10/100 Auto-MDIX Crossover Time When Auto-Negotiation is disabled, setting this bit extends the Auto-MDIX crossover time by 32 sample times (32 * 62 ms = 1984 ms). This allows the link to be established with a partner PHY that has Auto-Negotiation enabled. When Auto-Negotiation is enabled, this bit has no affect. It is recommended that this bit is set when disabling AN with Auto-MDIX enabled. R/W NASR Note 7 1b Bits Description Type Default |
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