LAN9252SLASHML datasheet(159/329 Pages) MICROCHIP

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DS00001909A-page 159

LAN9252

11.2.16.12 PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x)

This register is used to Enable EEE functionality and control NLP pulse generation and the Auto-MDIX Crossover Time

of the PHY.

Index (decimal): 16

Size:

16 bits

Bits

Description

Type

Default

EDPD TX NLP Enable

Enables the generation of a Normal Link Pulse (NLP) with a selectable inter-

val while in Energy Detect Power-Down. 0=disabled, 1=enabled.

The Energy Detect Power-Down (EDPWRDOWN) bit in the PHY x Mode

Control/Status Register (PHY_MODE_CONTROL_STATUS_x) needs to be

set in order to enter Energy Detect Power-Down mode and the PHY needs to

be in the Energy Detect Power-Down state in order for this bit to generate the

NLP.

The EDPD TX NLP Independent Mode bit of this register also needs to be set

when setting this bit.

R/W

NASR

Note 7

14:13

EDPD TX NLP Interval Timer Select

Specifies how often a NLP is transmitted while in the Energy Detect Power-

Down state.

00b: 1 s

01b: 768 ms

10b: 512 ms

11b: 256 ms

R/W

NASR

Note 7

00b

EDPD RX Single NLP Wake Enable

When set, the PHY will wake upon the reception of a single Normal Link

Pulse. When clear, the PHY requires two link pluses, within the interval spec-

ified below, in order to wake up.

Single NLP Wake Mode is recommended when connecting to “Green” net-

work devices.

R/W

NASR

Note 7

11:10

EDPD RX NLP Max Interval Detect Select

These bits specify the maximum time between two consecutive Normal Link

Pulses in order for them to be considered a valid wake up signal.

00b: 64 ms

01b: 256 ms

10b: 512 ms

11b: 1 s

R/W

NASR

Note 7

00b

9:4

RESERVED

EDPD TX NLP Independent Mode

When set, each PHY port independently detects power down for purposes of

the EDPD TX NLP function (via the EDPD TX NLP Enable bit of this register).

When cleared, both ports need to be in a power-down state in order to gener-

ate TX NLPs during energy detect power-down.

Normally set this bit when setting EDPD TX NLP Enable.

R/W

NASR

Note 7

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