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LAN9252/ML 数据表(PDF) 165 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 165 Page - Microchip Technology |
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165 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 165 LAN9252 11.2.16.16 PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x) Note 14: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg- ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set. Index (In Decimal): 25 Size: 16 bits Bits Description Type Default 15 TDR Enable 0 = TDR mode disabled 1 = TDR mode enabled Note: This bit self clears when TDR completes (TDR Channel Status goes high) R/W NASR SC Note 14 0b 14 TDR Analog to Digital Filter Enable 0 = TDR analog to digital filter disabled 1 = TDR analog to digital filter enabled (reduces noise spikes during TDR pulses) R/W NASR Note 14 0b 13:11 RESERVED RO - 10:9 TDR Channel Cable Type Indicates the cable type determined by the TDR test. 00 = Default 01 = Shorted cable condition 10 = Open cable condition 11 = Match cable condition R/W NASR Note 14 00b 8 TDR Channel Status When high, this bit indicates that the TDR operation has completed. This bit will stay high until reset or the TDR operation is restarted (TDR Enable = 1) R/W NASR Note 14 0b 7:0 TDR Channel Length This eight bit value indicates the TDR channel length during a short or open cable condition. Refer to Section 11.2.12.1, "Time Domain Reflectometry (TDR) Cable Diagnostics," on page 136 for additional information on the usage of this field. Note: This field is not valid during a match cable condition. The PHY x Cable Length Register (PHY_CABLE_LEN_x) must be used to determine cable length during a non-open/short (match) condition. Refer to Section 11.2.12, "Cable Diagnostics," on page 136 for additional information. R/W NASR Note 14 00h |
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