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LAN9252/ML 数据表(PDF) 199 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 199 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 199
LAN9252
12.4.6
DIGITAL I/O TIMING REQUIREMENTS
This section specifies the DIGIO[15:0], LATCH_IN and SOF input and output timings.
FIGURE 12-2:
ETHERCAT DIGITAL I/O INPUT TIMING DIAGRAM
FIGURE 12-3:
ETHERCAT DIGITAL I/O OUTPUT TIMING DIAGRAM
SOF
DIGIO[15:0]
tsof
tsofdatah
tsofdatav
LATCH_IN
tlatchin
tlatchindelay
tindatalatchs
tindatalatchh
SYNC0/1
tindatasyncs
tindatasynch
DIGIO[15:0]
OUTVALID
toutdatas
toutvaliddelay
toutvalid
WD_TRIG
twd_trig
twd_trigdata
OE_EXT
toe_extdata
EOF
teof
teofdata
SYNC0/1
tsyncdata



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