LAN9252SLASHML datasheet(203/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 203

LAN9252

12.9.1.1

EXTERNAL MII PHY CONNECTION

An external PHY is connected to the MII port as shown in Figure 12-5. The clock source for the Ethernet PHY and the

EtherCAT Slave must be the same. A 25 MHz output (MII_CLK25) is provided to be used as the reference clock for the

PHY. TX_CLK from the PHY is not connected since the EtherCAT Slave does not incorporate a TX FIFO. The TX signals

from the EtherCAT Slave may be delayed with respect to the CLK25 output by using TX shift compensation so that they

align properly as if they were driven by the PHY’s TX_CLK. MII timing is described in Section 12.9.7, "External PHY

Timing".

The Ethernet PHY should be connected to the EtherCAT Slave RST# pin so that the PHY is held in reset until the Eth-

erCAT Slave is ready. Otherwise, the far end Link Partner would detect valid link signals from the PHY and would “open”

its port assuming that the local EtherCAT Slave was ready.

The MII_MDC and MII_MDIO signals are connected between the EtherCAT slave and the PHY. MII_MDIO requires

an external pull-up. The management address of the external PHY must be set to 0 when chip_mode_strap[1:0] is equal

to 11b (3 port upstream mode) and to 2 when chip_mode_strap[1:0] is equal to 10b (3 port downstream mode).

LINK_STATUS from the PHY is an LED output which indicates that a 100 Mbit/s, Full Duplex link is active. The polarity

of the MII_LINK input of the EtherCAT slave is configurable.

The COL and CRS outputs from the PHY are not connected since EtherCAT operates in full-duplex mode.

The TX_ER input to the PHY is tied to system ground since the EtherCAT Slave never generates transmit errors.

12.9.1.2

BACK-TO-BACK CONNECTION

Two EtherCAT Slave devices can be connected using a back-to-back MII connection as shown in Figure 12-6. One

device is placed in 3 port upstream mode and the other in 3 port downstream mode.

The clock sources of each EtherCAT Slave may be different. The 25 MHz output (MII_CLK25) is provided to be used

as the RX_CLK input to the other device. The TX signals from each EtherCAT Slave may be delayed with respect to

the CLK25 output by using TX shift compensation so that they align properly to meet the RX timing requirement of the

other device. Back-to-back MII timing is described in Section 12.9.7, "External PHY Timing".

The MII_RXER signals are not used since the EtherCAT Slaves never generate errors.

The MII_MDIO and MII_MDC signals are not used since neither device contains a PHY register set. The MII_MDIO

pins require (separate) pull-ups so that a high value is returned when PHY register reads are attempted.

FIGURE 12-5:

ETHERCAT EXTERNAL PHY CONNECTION

0 or 2

0 ns

10 ns

20 ns

30 ns

VDDIO

LAN9252

MII_CLK25

MII_LINK

MII_RXCLK

MII_RXDV

MII_RXD[3:0]

MII_RXER

MII_TXEN

MII_TXD[3:0]

MII_MDIO

MII_MDC

OSCI

OSCO

TX shift

configuration

RST#

PHY

CLK25

LINK_STATUS

RX_CLK

RX_DV

RX_D[3:0]

RX_ER

TX_CLK

TX_EN

TX_D[3:0]

TX_ER

COL

CRS

MDIO

MDC

PHY_ADDR

RESET#

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