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LAN9252/ML 数据表(PDF) 204 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 204 Page - Microchip Technology |
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204 / 329 page  LAN9252 DS00001909A-page 204 2015 Microchip Technology Inc. MII_LINK may be tied active, if the two EtherCAT slaves are released from reset at about the same time. Otherwise, MII_LINK can be used to indicate to the partner that the device is not ready. 12.9.1.3 2 PORT OPERATION When configured for two port mode (chip_mode_strap[1:0] equal to 00b), port 2 is disabled. The port status is also shown in the Port 2 Configuration bits of the Port Descriptor Register and is set to a 01b (Not configured) when the device is configured for two port operation. 12.9.2 PORT 1 (INTERNAL PHY B) Port 1 of the EtherCAT core is always connected to internal PHY B. 12.9.3 PHY CONFIGURATION By default, the internal PHYs are configured for 100Mbps, full-duplex operation. Auto-Negotiation is enable for 100BASE-TX mode and disable for 100BASE-FX mode. The EtherCAT Core will also check and update the configura- tion if necessary. By default, the external PHY is configured for 100Mbps, full-duplex operation with Auto-Negotiation enabled. The Eth- erCAT Core will check and update the configuration if necessary. 12.9.4 PHY LINK STATUS The link status originates from the PHY’s link signal (internal or external). The EtherCAT Core also checks the PHY sta- tus to determine a proper link. By cyclically polling the PHYs, it checks that Auto-negotiation registers are configure properly, if a link is established, if Auto-Negotiation has finished successfully and if the link partner also used Auto-Nego- tiation. Link checking through the MII Management Interface (MI) is enabled via EEPROM and reflected in the MII Management Control/Status Register. FIGURE 12-6: ETHERCAT BACK-TO-BACK MII CONNECTION Note: MI link detection is disabled until the device is successfully configured from the EEPROM. The EEPROM setting for MI link detection is only taken at the first EEPROM loading after power-on or reset. Changing the EEPROM and manually reloading it will not affect the MI link detection enable status, even if the EEPROM could not be read initially. 10 ns 20 ns VDDIO 10 ns 20 ns VDDIO towards Master towards other salves LAN9252 MII_CLK25 MII_LINK MII_RXCLK MII_RXDV MII_RXD[3:0] MII_RXER MII_TXEN MII_TXD[3:0] MII_MDIO MII_MDC OSCI OSCO TX shift configuration (downstream mode) RST# LAN9252 MII_CLK25 MII_LINK MII_RXCLK MII_RXDV MII_RXD[3:0] MII_RXER MII_TXEN MII_TXD[3:0] MII_MDIO MII_MDC OSCI OSCO TX shift configuration (upstream mode) RST# |
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