LAN9252SLASHML datasheet(202/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 202

 2015 Microchip Technology Inc.

12.9

Port Interfaces

12.9.1

PORTS 0 AND 2 (INTERNAL PHY A OR EXTERNAL MII)

Port 0 of the EtherCAT Slave is connected to internal PHY A when chip_mode_strap[1:0] is not equal to 11b (2 port

mode or 3 port downstream mode). Port 0 is connected to the MII pins when chip_mode_strap[1:0] is equal to 11b (3

port upstream mode).

Port 2 of the EtherCAT Slave is connected to internal PHY A when chip_mode_strap[1:0] is equal to 11b (3 port

upstream mode). Port 2 is connected to the MII pins when chip_mode_strap[1:0] is equal to 10b (3 port downstream

mode).

PDI Configuration Register

(0150h)

Digital I/O Mode

[7:6] Output Data Sample Selection

1 / [7:6]

[5:4] Input Data Sample Selection

1 / [5:4]

[3] Watchdog Behavior

1 / [3]

[2] Unidirectional/Bidirectional Mode

1 / [2]

[1] OUTVALID Mode

1 / [1]

[0] OUTVALID Polarity

1 / [0]

PDI Configuration Register

(0150h)

HBI Mode

[7] HBI ALE Qualification

1 / [7]

[6] HBI Read/Write Mode

1 / [6]

[5] HBI Chip Select Polarity

1 / [5]

[4] HBI Read, Read/Write Polarity

1 / [4]

[3] HBI Write, Enable Polarity

1 / [3]

[2] HBI ALE Polarity

1 / [2]

[1:0] RESERVED (unused)

1 / [1:0]

Sync/Latch PDI Configuration Register

(0151h)

[7] SYNC1 Map

1 / [15]

[6] SYNC1/LATCH1 Configuration

1 / [14]

[5:4] SYNC1 Output Driver/Polarity

1 / [13:12]

[3] SYNC0 Map

1 / [11]

[2] SYNC0/LATCH0 Configuration

1 / [10]

[1:0] SYNC0 Output Driver/Polarity

1 / [9:8]

Pulse Length of SyncSignals Register

(0982h-0983h)

[15:0] Pulse length of SyncSignals

2 / [15:0]

Extended PDI Configuration Register

(0152h-0153h)

Digital I/O Mode

[15:8] RESERVED

3 / [15:8]

[7:0] I/O 15-0 Direction

3 / [7:0]

Extended PDI Configuration Register

(0152h-0153h)

SPI Mode

[15:8] I/O 15-0 Buffer Type

3 / [15:8]

[7:0] I/O 15-0 Direction

3 / [7:0]

Configured Station Alias Register

(0012h-0013h)

[15:0] Configured Station Alias Address

4 / [15:0]

MII Management Control/Status Register

(0510h-0511h)

[2] MI Link Detection

5 / [15]

ASIC Configuration Register (0142h-0143h)

[15] MI Link Detection

[14:8] RESERVED

5 / [14:8]

[7] MI Write Gigabit Register 9 Enable

5 / [7]

[6:0] RESERVED

5 / [6:0]

RESERVED Register (0144h-0145h)

[15:0] RESERVED

6 / [15:0]

TABLE 12-3:

ETHERCAT CORE EEPROM CONFIGURABLE REGISTERS

Bits

EEPROM

Word / [Bits]

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