LAN9252SLASHML datasheet(201/329 Pages) MICROCHIP

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DS00001909A-page 201

LAN9252

12.6

GPIOs

The EtherCAT Core provides 16 General Purpose Inputs (GPI[15:0]) and 16 General Purpose Outputs (GPO[15:0]) The

General Purpose Output Register is used to control the output value. The General Purpose Input Register is used to

read the input value.

Each 2-bit pair is configurable as input, push-pull output or open-drain output. The direction and buffer type are deter-

mined by the Extended PDI Configuration Register. Bits 7:0 control the direction of the pairs (bit 0 for GPIO[1:0], bit 1

for GPIO[3:2], etc.). A value of 1 selects the output direction. Bits 15:8 control the output type (bit 8 for GPIO[1:0], bit 9

for GPIO[3:2], etc.). A value of 1 selects the open-drain. The Extended PDI Configuration Register is initialized from the

contents of the EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional infor-

mation.

12.7

User RAM

A 128 byte user RAM is located at 0F80h-0FFFh. The default values within this RAM are undefined for all addresses.

12.8

EEPROM Configurable Registers

The following registers are configurable via EEPROM. Refer to the corresponding register definition for details on each

bit function.

Note:

When GPIOs are not available due to chip configuration, the General Purpose Output Register remains R/

W, but has no effect. When GPIOs are not available due to chip configuration, the General Purpose Input

Note:

The Extended PDI Configuration Register is also used for the Digital I/O PDI direction. However, GPIOs

are not used during Digital I/O mode.

Note:

Reserved bits must be written as 0 unless otherwise noted.

TABLE 12-3:

ETHERCAT CORE EEPROM CONFIGURABLE REGISTERS

Bits

EEPROM

Word / [Bits]

PDI Control Register

(0140h)

[7:0] Process Data Interface

0 / [7:0]

ESC Configuration Register

(0141h)

[7] (unused)

0 / [15]

[6] Enhanced Link Port 2

0 / [14]

[5] Enhanced Link Port 1

0 / [13]

[4] Enhanced Link Port 0

0 / [12]

[3] Distributed Clocks Latch In Unit

Note:

Bit 3 is NOT set by EEPROM

[2] Distributed Clocks SYNC Out Unit

Note:

Bit 2 is NOT set by EEPROM

[1] Enhanced Link Detection All Ports

0 / [9]

[0] Device Emulation

(control of AL Status Register)

0 / [8]

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