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LAN9252/ML 数据表(PDF) 200 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 200 Page - Microchip Technology |
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200 / 329 page  LAN9252 DS00001909A-page 200 2015 Microchip Technology Inc. 12.5 Host Interface PDI The Host Interface PDI is used for systems with a host controller that use either a HBI or SPI chip-level host interface. The values in the PDI Configuration Register and the Extended PDI Configuration Register reflect the value from EEPROM. The value in the PDI Configuration Register is used for Host Interface modes to configure the HBI. The value in the Extended PDI Configuration Register is used if GPIOs are enabled (SPI w/GPIO). The PDI Configuration Register and Extended PDI Configuration Register are initialized from the contents of the EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. FIGURE 12-4: ETHERCAT DIGITAL I/O BI-DIRECTIONAL TIMING DIAGRAM TABLE 12-2: ETHERCAT DIGITAL I/O TIMING VALUES Symbol Description Min Typ Max Units tindatasyncs Input data setup to SYNC0/1 rising 10 - - ns tindatasynch Input data hold from SYNC0/1 rising 0 - - ns tindatalatchs Input data setup to LATCH_IN rising 8 - - ns tindatalatchh Input data hold from LATCH_IN rising 4 - - ns tlatchin LATCH_IN high time 8 - - ns tlatchindelay time between consecutive input events 440 - - ns tsof SOF high time 35 - 45 ns tsofdatav Input data valid after SOF active, so that input data can be read in the same frame -- 1.2 s tsofdatah Input data hold after SOF active, so that input data can be read in the same frame 1.6 - - s toutdatas Output data setup to OUTVALID rising 65 - - ns toutdatah Output data hold from OUTVALID falling 65 - - ns toutvalid OUTVALID high time 75 - 85 ns toutvaliddelay time between consecutive output events 320 - - ns teof EOF high time 35 - 45 ns teofdata Output data valid after EOF -- 35 ns twd_trig WD_TRIG high time 35 - 45 ns twd_trigdata Output data valid after WD_TRIG -- 35 ns tsyncdata Output data valid after SYNC0/1 -- 25 ns toe_extdata OE_EXT to data low 0 - 15 ns tbidirdelay time between consecutive input or output events 440 - - ns DIGIO[15:0] OUTVALID toutdatas toutvalid Output Data Input Data toutdatah Input Data input events input events allowed input events allowed no input events allowed tbidirdelay tbidirdelay |
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