LAN9252SLASHML datasheet(126/329 Pages) MICROCHIP

126 / 329 page

LAN9252

DS00001909A-page 126

 2015 Microchip Technology Inc.

Once Auto-Negotiation has completed, information about the resolved link and the results of the negotiation process

are reflected in the Speed Indication bits in the PHY x Special Control/Status Register (PHY_SPECIAL_CON-

TROL_STATUS_x), as well as the PHY x Auto-Negotiation Link Partner Base Page Ability Register

(PHY_AN_LP_BASE_ABILITY_x). The Auto-Negotiation protocol is a purely physical layer activity and proceeds inde-

pendently of the MAC controller.

The following blocks are activated during an Auto-Negotiation session:

• Auto-Negotiation (digital)

• 100M ADC (analog)

• 100M PLL (analog)

• 100M equalizer/BLW/clock recovery (DSP)

• 10M SQUELCH (analog)

• 10M PLL (analog)

• 10M Transmitter (analog)

When enabled, Auto-Negotiation is started by the occurrence of any of the following events:

• Power-On Reset (POR)

• Hardware reset (RST#)

• PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the PHY x Basic Control Register

(PHY_BASIC_CONTROL_x))

• PHY Power-down reset (Section 11.2.8, "PHY Power-Down Modes," on page 131)

• PHY Link status down (bit 2 of the PHY x Basic Status Register (PHY_BASIC_STATUS_x) is cleared)

• Setting the PHY x Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 high (auto-neg restart)

• EtherCAT System Reset

On detection of one of these events, the transceiver begins Auto-Negotiation by transmitting bursts of Fast Link Pulses

(FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal Link Pulses and can pass

uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered

pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent,

contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.

The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28.

In summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It

advertises its technology ability according to the bits set in the PHY x Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x).

There are 4 possible matches of the technology abilities. In the order of priority these are:

• 100M Full Duplex (Highest priority)

• 100M Half Duplex

• 10M Full Duplex

• 10M Half Duplex (Lowest priority)

If the full capabilities of the transceiver are advertised (100M, full-duplex), and if the link partner is capable of 10M and

100M, then Auto-Negotiation selects 100M as the highest performance mode. If the link partner is capable of half and

full-duplex modes, then Auto-Negotiation selects full-duplex as the highest performance mode.

Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any dif-

ference in the main content of the link code words at this time will cause Auto-Negotiation to re-start. Auto-Negotiation

will also re-start if not all of the required FLP bursts are received.

Writing the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) bits [8:5] allows software control of the

capabilities advertised by the transceiver. Writing the PHY x Auto-Negotiation Advertisement Register (PHY_AN_AD-

V_x) does not automatically re-start Auto-Negotiation. The Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY x

Basic Control Register (PHY_BASIC_CONTROL_x) must be set before the new abilities will be advertised. Auto-Nego-

tiation can also be disabled via software by clearing the Auto-Negotiation Enable (PHY_AN) bit of the PHY x Basic Con-

trol Register (PHY_BASIC_CONTROL_x).

Note:

Refer to Section 6.2, "Resets," on page 38 for information on these and other system resets.

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