LAN9252SLASHML datasheet(127/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 127

LAN9252

11.2.4.1

Parallel Detection

If the device is connected to a device lacking the ability to Auto-Negotiate (i.e. no FLPs are detected), it is able to deter-

mine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is

presumed to be half-duplex per the IEEE 802.3 standard. This ability is known as “Parallel Detection.” This feature

ensures interoperability with legacy link partners. If a link is formed via parallel detection, then the Link Partner Auto-

Negotiation Able bit of the PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is cleared to indicate that the

link partner is not capable of Auto-Negotiation. If a fault occurs during parallel detection, the Parallel Detection Fault bit

of the PHY x Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is set.

The PHY x Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) is used to store

the Link Partner Ability information, which is coded in the received FLPs. If the link partner is not Auto-Negotiation capa-

ble, then this register is updated after completion of parallel detection to reflect the speed capability of the link partner.

11.2.4.2

Restarting Auto-Negotiation

Auto-Negotiation can be re-started at any time by setting the Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY

x Basic Control Register (PHY_BASIC_CONTROL_x). Auto-Negotiation will also re-start if the link is broken at any time.

A broken link is caused by signal loss. This may occur because of a cable break, or because of an interruption in the

signal transmitted by the Link Partner. Auto-Negotiation resumes in an attempt to determine the new link configuration.

If the management entity re-starts Auto-Negotiation by setting the Restart Auto-Negotiation (PHY_RST_AN) bit of the

PHY x Basic Control Register (PHY_BASIC_CONTROL_x), the device will respond by stopping all transmission/receiv-

ing operations. Once the internal break_link_time is completed in the Auto-Negotiation state-machine (approximately

1200ms), Auto-Negotiation will re-start. In this case, the link partner will have also dropped the link due to lack of a

received signal, so it too will resume Auto-Negotiation.

11.2.4.3

Disabling Auto-Negotiation

Auto-Negotiation can be disabled by clearing the Auto-Negotiation Enable (PHY_AN) bit of the PHY x Basic Control

the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) (Speed Select LSB (PHY_SPEED_SEL_LSB) and

Duplex Mode (PHY_DUPLEX)). These bits are ignored when Auto-Negotiation is enabled.

11.2.4.4

Half Vs. Full-Duplex

Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle net-

work traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If

data is received while the transceiver is transmitting, a collision results.

In full-duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode, CRS responds

only to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled.

11.2.5

HP AUTO-MDIX

HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP interconnect cable without

consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable or a cross-over patch cable,

as shown in Figure 11-4, the transceiver is capable of configuring the TXPx/TXNx and RXPx/RXNx twisted pair pins for

correct transceiver operation.

The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs

are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and

termination of an Auto-MDIX design.

Software based control of the Auto-MDIX function may be performed using the Auto-MDIX Control (AMDIXCTRL) bit of

the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL

is set to 1, the Auto-MDIX capability is determined by the Auto-MDIX Enable (AMDIXEN) and Auto-MDIX State (AMDIX-

STATE) bits of the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x).

Note:

Auto-MDIX is not used for 100BASE-FX mode.

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