LAN9252SLASHML datasheet(129/329 Pages) MICROCHIP

129 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 129

LAN9252

11.2.7.1

Primary Interrupt Mode

The Primary interrupt mode is the default interrupt mode. The Primary interrupt mode is always selected after power-up

or hard reset. In this mode, to enable an interrupt, set the corresponding mask bit in the PHY x Interrupt Mask Register

(PHY_INTERRUPT_MASK_x) (see Table 11-2). When the event to assert an interrupt is true, the internal interrupt sig-

nal will be asserted. When the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be

de-asserted.

Note 1:

LINKSTAT is the internal link status and is not directly available in any register bit.

Note 2:

WOL_INT is defined as bits 7:4 in the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) ANDed

with bits 3:0 of the same register, with the resultant 4 bits OR’ed together.

TABLE 11-2:

INTERRUPT MANAGEMENT TABLE

Mask

Interrupt Source Flag

Interrupt Source

Event to Assert

interrupt

Event to

De-assert interrupt

30.9

29.9

Link Up

LINKSTAT

See Note 1

Link Status

Rising LINK-

STAT

Falling LINKSAT or

Reading register 29

30.8

29.8

Wake on LAN

WOL_INT

See Note 2

Enabled

WOL event

Rising WOL_INT

Falling WOL_INT or

Reading register 29

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

(Note 3)

Falling 17.1 or

Reading register 29

30.6

29.6

Auto-Negotia-

tion complete

1.5

Auto-Negoti-

ate Com-

plete

Rising 1.5

Falling 1.5 or

Reading register 29

30.5

29.5

Remote Fault

Detected

1.4

Remote

Fault

Rising 1.4

Falling 1.4, or

Reading register 1 or

Reading register 29

30.4

29.4

Link Down

1.2

Link Status

Falling 1.2

Reading register 1 or

Reading register 29

30.3

29.3

Auto-Negotia-

tion LP Acknowl-

edge

5.14

Acknowl-

edge

Rising 5.14

Falling 5.14 or

Reading register 29

30.2

29.2

Parallel Detec-

tion Fault

6.4

Parallel

Detection

Fault

Rising 6.4

Falling 6.4 or

Reading register 6, or

Reading register 29, or

Re-Auto Negotiate or

Link down

30.1

29.1

Auto-Negotia-

tion Page

Received

6.1

Page

Received

Rising 6.1

Falling 6.1 or

Reading register 6, or

Reading register 29, or

Re-Auto Negotiate, or

Link down.

LAN9252/ML 数据表(PDF) 129 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 129 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

LAN9252/ML 数据表(PDF) 129 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 129 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载